From patchwork Tue May 21 15:45:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Erwan Le Ray X-Patchwork-Id: 164733 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp1768202ili; Tue, 21 May 2019 08:46:39 -0700 (PDT) X-Google-Smtp-Source: APXvYqyLJeS9f9xuIOxU4dTLU4DewDtbtSpJcoq95w0ZszmtwowVTMe/qYgFOEsYrJwJgBQrpJM2 X-Received: by 2002:a63:1344:: with SMTP id 4mr82021797pgt.448.1558453599809; Tue, 21 May 2019 08:46:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558453599; cv=none; d=google.com; s=arc-20160816; b=IHabFyUBrgrMS4N3OZ8/UIFQwrIAyxuQCCcngB6aX9wxdydyhr1edL2jAt5rytWEgb LN6axeZPCQTmsafy7Rl7NZCDXqXudSkJMKtX8bM6zDIsRQvI/PsZlZ0RgrkCa8PqJK6p uqENNorx80TBBcGaeglgTmuSLyHW+rTqCMl48L/lHYxUzIfTYhCaQ8bZOBhXeDNQSKVS suuBZTlnm7SN04bNwqkJwJcCJKiFluNNt7j+z9UM/6kNbgNYPHUU9Fp7zAPSmtJFkPgU 7DtFbl0G/p/PtDRn889dVGnjfVcGeLz5JC/kqjWodzfP93gMhrO7JLbeuybSeTcTXIF8 ETeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=dckJd0TpTuYSyAzItwV1CCOJi+gwS5cSNQ1t2XCMxko=; b=f+GWiysIkJtyhx/I4GhY2Vkbff5dmV9Z0oKwMwFGJeS0fDC3TEsmt9ethY0SvfBf1N WWu+f9d7OooFHAt1LN63X4ZZNhANeY5TIkcwKChBj7ZuBSWwYGSCApzuo9LY0+5BpIJX fcEB4ZyJcFP4OnyxAWHX381tOYug/nXQ9FmMDgYYXbUq5RPwk2VtY1YHGzIoQI+7lU3Q 42siK/iOwF0XqY+KSK2qX8Fc4VDe2b5OwjBZrQP4xVe1P/8/6Lnxk6GX7hGOcgSpQpRW JQIJZTVFR86DC4RC10hTCikTBT/0GEZRAyLPIjNeCsm2z2faEbyvBSqVu4VvZnuoNbtf gX4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b=TgRfIKBE; spf=pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id co12si22260996plb.384.2019.05.21.08.46.39; Tue, 21 May 2019 08:46:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b=TgRfIKBE; spf=pass (google.com: best guess record for domain of linux-serial-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728324AbfEUPqj (ORCPT + 1 other); Tue, 21 May 2019 11:46:39 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:2446 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728137AbfEUPqj (ORCPT ); Tue, 21 May 2019 11:46:39 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x4LFaPZb018181; Tue, 21 May 2019 17:46:23 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=dckJd0TpTuYSyAzItwV1CCOJi+gwS5cSNQ1t2XCMxko=; b=TgRfIKBE+t3bCcXLVaNETIeBSG0XdkKbtAnjgEyP62B3LfDR5m9VXVFFjo9GZXQ0dDQe xktcCgjoU90ckS8rhHyAIPwRStE+LGoZ3Ip//U8gzn5pQjlwd4v6+dmy7A4F8/28RxTI HamghdvFQO2cAvoI/DhPbX02e1vTnQNK9NXqtG0MOQuft7luStomJ0onOgTxVGp6ku95 kzZ5EDNeQJ0TzoqIUDjapz9N7/3wzkNlvLqrKPew8/GSSd1rO9IWdtVRf99PHp4r7Zfi MEjaI7STsaofbQo9DidmeVnQ/g5SRA0PVx7nE0kc+dpqdFrV6K2Qvj3bCo4yByZs+0Kq 9w== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2sj7742uaa-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 21 May 2019 17:46:23 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 48EDA38; Tue, 21 May 2019 15:46:22 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas22.st.com [10.75.90.92]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2DA4F2CEA; Tue, 21 May 2019 15:46:22 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.46) by Safex1hubcas22.st.com (10.75.90.92) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 21 May 2019 17:46:22 +0200 Received: from localhost (10.201.23.31) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 21 May 2019 17:46:21 +0200 From: Erwan Le Ray To: Greg Kroah-Hartman , Jiri Slaby , Maxime Coquelin , "Alexandre Torgue" CC: , , , , "Erwan Le Ray" , Fabrice Gasnier Subject: [PATCH 1/7] serial: stm32: fix word length configuration Date: Tue, 21 May 2019 17:45:41 +0200 Message-ID: <1558453547-22866-2-git-send-email-erwan.leray@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1558453547-22866-1-git-send-email-erwan.leray@st.com> References: <1558453547-22866-1-git-send-email-erwan.leray@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.31] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-21_03:, , signatures=0 Sender: linux-serial-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org STM32 supports either: - 8 and 9 bits word length (including parity bit) for stm32f4 compatible devices - 7, 8 and 9 bits word length (including parity bit) for stm32f7 and stm32h7 compatible devices. As a consequence STM32 supports the following termios configurations: - CS7 with parity bit, and CS8 (with or without parity bit) for stm32f4 compatible devices. - CS6 with parity bit, CS7 and CS8 (with or without parity bit) for stm32f7 and stm32h7 compatible devices. This patch is fixing word length by configuring correctly the SoC with supported configurations. Fixes: ada8618ff3bf ("serial: stm32: adding support for stm32f7") Signed-off-by: Erwan Le Ray -- 1.9.1 diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c index e8d7a7b..e832185 100644 --- a/drivers/tty/serial/stm32-usart.c +++ b/drivers/tty/serial/stm32-usart.c @@ -599,6 +599,36 @@ static void stm32_shutdown(struct uart_port *port) free_irq(port->irq, port); } +unsigned int stm32_get_databits(struct ktermios *termios) +{ + unsigned int bits; + + tcflag_t cflag = termios->c_cflag; + + switch (cflag & CSIZE) { + /* + * CSIZE settings are not necessarily supported in hardware. + * CSIZE unsupported configurations are handled here to set word length + * to 8 bits word as default configuration and to print debug message. + */ + case CS5: + bits = 5; + break; + case CS6: + bits = 6; + break; + case CS7: + bits = 7; + break; + /* default including CS8 */ + default: + bits = 8; + break; + } + + return bits; +} + static void stm32_set_termios(struct uart_port *port, struct ktermios *termios, struct ktermios *old) { @@ -606,7 +636,7 @@ static void stm32_set_termios(struct uart_port *port, struct ktermios *termios, struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; struct stm32_usart_config *cfg = &stm32_port->info->cfg; struct serial_rs485 *rs485conf = &port->rs485; - unsigned int baud; + unsigned int baud, bits; u32 usartdiv, mantissa, fraction, oversampling; tcflag_t cflag = termios->c_cflag; u32 cr1, cr2, cr3; @@ -632,16 +662,28 @@ static void stm32_set_termios(struct uart_port *port, struct ktermios *termios, if (cflag & CSTOPB) cr2 |= USART_CR2_STOP_2B; + bits = stm32_get_databits(termios); + if (cflag & PARENB) { + bits++; cr1 |= USART_CR1_PCE; - if ((cflag & CSIZE) == CS8) { - if (cfg->has_7bits_data) - cr1 |= USART_CR1_M0; - else - cr1 |= USART_CR1_M; - } } + /* + * Word length configuration: + * CS8 + parity, 9 bits word aka [M1:M0] = 0b01 + * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10 + * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00 + * M0 and M1 already cleared by cr1 initialization. + */ + if (bits == 9) + cr1 |= USART_CR1_M0; + else if ((bits == 7) && cfg->has_7bits_data) + cr1 |= USART_CR1_M1; + else if (bits != 8) + dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" + , bits); + if (cflag & PARODD) cr1 |= USART_CR1_PS; diff --git a/drivers/tty/serial/stm32-usart.h b/drivers/tty/serial/stm32-usart.h index 6f294e2..a70aa50 100644 --- a/drivers/tty/serial/stm32-usart.h +++ b/drivers/tty/serial/stm32-usart.h @@ -151,8 +151,7 @@ struct stm32_usart_info stm32h7_info = { #define USART_CR1_PS BIT(9) #define USART_CR1_PCE BIT(10) #define USART_CR1_WAKE BIT(11) -#define USART_CR1_M BIT(12) -#define USART_CR1_M0 BIT(12) /* F7 */ +#define USART_CR1_M0 BIT(12) /* F7 (CR1_M for F4) */ #define USART_CR1_MME BIT(13) /* F7 */ #define USART_CR1_CMIE BIT(14) /* F7 */ #define USART_CR1_OVER8 BIT(15)