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Tue, 8 Dec 2020 04:56:09 +0000 From: Yash Shah To: linux-spi@vger.kernel.org, linux-serial@vger.kernel.org, linux-pwm@vger.kernel.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org Cc: broonie@kernel.org, gregkh@linuxfoundation.org, aou@eecs.berkeley.edu, lee.jones@linaro.org, u.kleine-koenig@pengutronix.de, thierry.reding@gmail.com, andrew@lunn.ch, peter@korsgaard.com, paul.walmsley@sifive.com, palmer@dabbelt.com, robh+dt@kernel.org, bgolaszewski@baylibre.com, linus.walleij@linaro.org, Yash Shah Subject: [PATCH v2 1/9] dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC Date: Tue, 8 Dec 2020 10:25:33 +0530 Message-Id: <1607403341-57214-2-git-send-email-yash.shah@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1607403341-57214-1-git-send-email-yash.shah@sifive.com> References: <1607403341-57214-1-git-send-email-yash.shah@sifive.com> X-Originating-IP: [159.117.144.156] X-ClientProxiedBy: PN1PR0101CA0041.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:c::27) To BY5PR13MB4453.namprd13.prod.outlook.com (2603:10b6:a03:1d1::19) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from osubuntu003.open-silicon.com (159.117.144.156) by PN1PR0101CA0041.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:c::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3632.17 via Frontend Transport; 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Signed-off-by: Yash Shah Reviewed-by: Rob Herring Reviewed-by: Bin Meng --- Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index c6925e0..eb6843f 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -28,11 +28,17 @@ properties: - items: - enum: - sifive,rocket0 + - sifive,bullet0 - sifive,e5 + - sifive,e7 - sifive,e51 + - sifive,e71 - sifive,u54-mc + - sifive,u74-mc - sifive,u54 + - sifive,u74 - sifive,u5 + - sifive,u7 - const: riscv - const: riscv # Simulator only description: