From patchwork Mon Sep 13 17:38:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 511412 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73434C433F5 for ; Mon, 13 Sep 2021 17:39:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 608C6610CF for ; Mon, 13 Sep 2021 17:39:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344446AbhIMRkQ (ORCPT ); Mon, 13 Sep 2021 13:40:16 -0400 Received: from inva020.nxp.com ([92.121.34.13]:43952 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242897AbhIMRju (ORCPT ); Mon, 13 Sep 2021 13:39:50 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 0CA751A0397; Mon, 13 Sep 2021 19:38:33 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id EA37D1A010C; Mon, 13 Sep 2021 19:38:32 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 131AA20363; Mon, 13 Sep 2021 19:38:32 +0200 (CEST) From: Abel Vesa To: Rob Herring , Dong Aisheng , Shawn Guo , Sascha Hauer , Fabio Estevam , "catalin.marinas@arm.com" , Will Deacon , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Georgi Djakov , Adrian Hunter , Ulf Hansson , Ahmad Fatoum Cc: Pengutronix Kernel Team , linux-serial@vger.kernel.org, NXP Linux Team , Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Abel Vesa Subject: [RFC 12/19] arm64: dts: imx8mq: Add fsl, icc-id property to ddrc node Date: Mon, 13 Sep 2021 20:38:07 +0300 Message-Id: <1631554694-9599-13-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1631554694-9599-1-git-send-email-abel.vesa@nxp.com> References: <1631554694-9599-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org The fsl,icc-id property here is used to link the icc node registered by the imx8mq interconnect driver with the ddrc device. Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 4066b1612655..8ddbeaddf55a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1552,10 +1552,12 @@ ddrc: memory-controller@3d400000 { compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc"; reg = <0x3d400000 0x400000>; clock-names = "core", "pll", "alt", "apb"; + fsl,icc-id = ; clocks = <&clk IMX8MQ_CLK_DRAM_CORE>, <&clk IMX8MQ_DRAM_PLL_OUT>, <&clk IMX8MQ_CLK_DRAM_ALT>, <&clk IMX8MQ_CLK_DRAM_APB>; + #interconnect-cells = <0>; }; ddr-pmu@3d800000 {