From patchwork Mon Sep 13 17:38:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 510148 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E29F8C43217 for ; Mon, 13 Sep 2021 17:39:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D1BC5610D1 for ; Mon, 13 Sep 2021 17:39:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245594AbhIMRkg (ORCPT ); Mon, 13 Sep 2021 13:40:36 -0400 Received: from inva021.nxp.com ([92.121.34.21]:59160 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243866AbhIMRjx (ORCPT ); Mon, 13 Sep 2021 13:39:53 -0400 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 882BC2005D5; Mon, 13 Sep 2021 19:38:36 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 7060A2005AC; Mon, 13 Sep 2021 19:38:36 +0200 (CEST) Received: from fsr-ub1664-175.ea.freescale.net (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id A25C620363; Mon, 13 Sep 2021 19:38:35 +0200 (CEST) From: Abel Vesa To: Rob Herring , Dong Aisheng , Shawn Guo , Sascha Hauer , Fabio Estevam , "catalin.marinas@arm.com" , Will Deacon , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Georgi Djakov , Adrian Hunter , Ulf Hansson , Ahmad Fatoum Cc: Pengutronix Kernel Team , linux-serial@vger.kernel.org, NXP Linux Team , Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Abel Vesa Subject: [RFC 16/19] arm64: dts: imx8mq: Add interconnect properties to icc consumer nodes Date: Mon, 13 Sep 2021 20:38:11 +0300 Message-Id: <1631554694-9599-17-git-send-email-abel.vesa@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1631554694-9599-1-git-send-email-abel.vesa@nxp.com> References: <1631554694-9599-1-git-send-email-abel.vesa@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org We add all the properties necessary to control the interconnect based on the required rates all the way from consumers to the dram. The fsl,icc-rate specifies the minimum required rate the consumer needs in order to operate. For now, only the fec, usdhc1 and usdhc2 are added as consumers. Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 5a73ebda6bb3..0489f7416993 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1215,6 +1215,9 @@ usdhc1: mmc@30b40000 { "fsl,imx7d-usdhc"; reg = <0x30b40000 0x10000>; interrupts = ; + interconnects = <&icc IMX8MQ_ICM_USDHC1 &icc IMX8MQ_ICS_DRAM>; + interconnect-names = "path"; + fsl,icc-rate = <266666>; clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, <&clk IMX8MQ_CLK_USDHC1_ROOT>; @@ -1230,6 +1233,9 @@ usdhc2: mmc@30b50000 { "fsl,imx7d-usdhc"; reg = <0x30b50000 0x10000>; interrupts = ; + interconnects = <&icc IMX8MQ_ICM_USDHC2 &icc IMX8MQ_ICS_DRAM>; + interconnect-names = "path"; + fsl,icc-rate = <266666>; clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, <&clk IMX8MQ_CLK_USDHC2_ROOT>; @@ -1272,6 +1278,9 @@ fec1: ethernet@30be0000 { , , ; + interconnects = <&icc IMX8MQ_ICM_ENET &icc IMX8MQ_ICS_DRAM>; + interconnect-names = "path"; + fsl,icc-rate = <800000>; clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>, <&clk IMX8MQ_CLK_ENET1_ROOT>, <&clk IMX8MQ_CLK_ENET_TIMER>,