diff mbox series

[11/16] dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver

Message ID 20210514192218.13022-12-prabhakar.mahadev-lad.rj@bp.renesas.com
State New
Headers show
Series Add new Renesas RZ/G2L SoC and Renesas RZ/G2L SMARC EVK support | expand

Commit Message

Prabhakar Mahadev Lad May 14, 2021, 7:22 p.m. UTC
Document the device tree bindings of the Renesas RZ/G2L SoC clock
driver in Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../bindings/clock/renesas,rzg2l-cpg.yaml     | 80 +++++++++++++++++++
 1 file changed, 80 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

Comments

Rob Herring May 18, 2021, 1:35 a.m. UTC | #1
On Fri, 14 May 2021 20:22:13 +0100, Lad Prabhakar wrote:
> Document the device tree bindings of the Renesas RZ/G2L SoC clock

> driver in Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml.

> 

> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

> ---

>  .../bindings/clock/renesas,rzg2l-cpg.yaml     | 80 +++++++++++++++++++

>  1 file changed, 80 insertions(+)

>  create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

> 


Reviewed-by: Rob Herring <robh@kernel.org>
Geert Uytterhoeven May 21, 2021, 3:04 p.m. UTC | #2
Hi Prabhakar,

On Fri, May 14, 2021 at 9:23 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Document the device tree bindings of the Renesas RZ/G2L SoC clock

> driver in Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml.

>

> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>


Thanks for your patch!

> --- /dev/null

> +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

> @@ -0,0 +1,80 @@

> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

> +%YAML 1.2

> +---

> +$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"

> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"

> +

> +title: Renesas RZ/G2L Clock Pulse Generator / Module Stop and Software Reset


(Module Standby Mode
> +

> +maintainers:

> +  - Geert Uytterhoeven <geert+renesas@glider.be>

> +

> +description: |

> +  On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and MSTP

> +  (Module Stop and Software Reset) share the same register block.

> +

> +  They provide the following functionalities:

> +    - The CPG block generates various core clocks,

> +    - The MSTP block provides two functions:

> +        1. Module Stop, providing a Clock Domain to control the clock supply

> +           to individual SoC devices,

> +        2. Reset Control, to perform a software reset of individual SoC devices.

> +

> +properties:

> +  compatible:

> +    const: renesas,r9a07g044l-cpg  # RZ/G2L


renesas,r9a07g044-cpg?

I believe it's the same block on RZ/G2L ('044l) and RZ/G2LC ('044c).

> +  '#clock-cells':

> +    description: |

> +      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"

> +        and a core clock reference, as defined in

> +        <dt-bindings/clock/*-cpg-mssr.h>


<dt-bindings/clock/r9a07g044l-cpg.h>

> +      - For module clocks, the two clock specifier cells must be "CPG_MOD" and

> +        a module number, as defined in the datasheet.


Also in <dt-bindings/clock/r9a07g044l-cpg.h>?

> +    const: 2

> +

> +  '#power-domain-cells':

> +    description:

> +      SoC devices that are part of the CPG/MSTP Clock Domain and can be

> +      power-managed through Module Stop should refer to the CPG device node

> +      in their "power-domains" property, as documented by the generic PM Domain

> +      bindings in Documentation/devicetree/bindings/power/power-domain.yaml.

> +    const: 0

> +

> +  '#reset-cells':

> +    description:

> +      The single reset specifier cell must be the module number, as defined in

> +      the datasheet.


Also in <dt-bindings/clock/r9a07g044l-cpg.h>?

> +    const: 1


Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Prabhakar May 21, 2021, 6:42 p.m. UTC | #3
Hi Geert,

Thank you for the review.

On Fri, May 21, 2021 at 4:04 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>

> Hi Prabhakar,

>

> On Fri, May 14, 2021 at 9:23 PM Lad Prabhakar

> <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:

> > Document the device tree bindings of the Renesas RZ/G2L SoC clock

> > driver in Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml.

> >

> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

>

> Thanks for your patch!

>

> > --- /dev/null

> > +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

> > @@ -0,0 +1,80 @@

> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

> > +%YAML 1.2

> > +---

> > +$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"

> > +$schema: "http://devicetree.org/meta-schemas/core.yaml#"

> > +

> > +title: Renesas RZ/G2L Clock Pulse Generator / Module Stop and Software Reset

>

> (Module Standby Mode

> > +

> > +maintainers:

> > +  - Geert Uytterhoeven <geert+renesas@glider.be>

> > +

> > +description: |

> > +  On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and MSTP

> > +  (Module Stop and Software Reset) share the same register block.

> > +

> > +  They provide the following functionalities:

> > +    - The CPG block generates various core clocks,

> > +    - The MSTP block provides two functions:

> > +        1. Module Stop, providing a Clock Domain to control the clock supply

> > +           to individual SoC devices,

> > +        2. Reset Control, to perform a software reset of individual SoC devices.

> > +

> > +properties:

> > +  compatible:

> > +    const: renesas,r9a07g044l-cpg  # RZ/G2L

>

> renesas,r9a07g044-cpg?

>

As some IP blocks present in RZ/G2L aren't present in RZ/G2LC clock
handling will differ so as a result SoC specific compatible string is
added.

> I believe it's the same block on RZ/G2L ('044l) and RZ/G2LC ('044c).

>

> > +  '#clock-cells':

> > +    description: |

> > +      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"

> > +        and a core clock reference, as defined in

> > +        <dt-bindings/clock/*-cpg-mssr.h>

>

> <dt-bindings/clock/r9a07g044l-cpg.h>

>

Indeed

> > +      - For module clocks, the two clock specifier cells must be "CPG_MOD" and

> > +        a module number, as defined in the datasheet.

>

> Also in <dt-bindings/clock/r9a07g044l-cpg.h>?

>

Agreed.

> > +    const: 2

> > +

> > +  '#power-domain-cells':

> > +    description:

> > +      SoC devices that are part of the CPG/MSTP Clock Domain and can be

> > +      power-managed through Module Stop should refer to the CPG device node

> > +      in their "power-domains" property, as documented by the generic PM Domain

> > +      bindings in Documentation/devicetree/bindings/power/power-domain.yaml.

> > +    const: 0

> > +

> > +  '#reset-cells':

> > +    description:

> > +      The single reset specifier cell must be the module number, as defined in

> > +      the datasheet.

>

> Also in <dt-bindings/clock/r9a07g044l-cpg.h>?

>

Agreed.

Cheers,
Prabhakar

> > +    const: 1

>

> Gr{oetje,eeting}s,

>

>                         Geert

>

> --

> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

>

> In personal conversations with technical people, I call myself a hacker. But

> when I'm talking to journalists I just say "programmer" or something like that.

>                                 -- Linus Torvalds
Geert Uytterhoeven May 27, 2021, 11:51 a.m. UTC | #4
Hi Prabhakar,

On Fri, May 21, 2021 at 8:43 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Fri, May 21, 2021 at 4:04 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:

> > On Fri, May 14, 2021 at 9:23 PM Lad Prabhakar

> > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:

> > > Document the device tree bindings of the Renesas RZ/G2L SoC clock

> > > driver in Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml.

> > >

> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

> > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

> >

> > Thanks for your patch!

> >

> > > --- /dev/null

> > > +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

> > > @@ -0,0 +1,80 @@

> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

> > > +%YAML 1.2

> > > +---

> > > +$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"

> > > +$schema: "http://devicetree.org/meta-schemas/core.yaml#"

> > > +

> > > +title: Renesas RZ/G2L Clock Pulse Generator / Module Stop and Software Reset

> >

> > (Module Standby Mode

> > > +

> > > +maintainers:

> > > +  - Geert Uytterhoeven <geert+renesas@glider.be>

> > > +

> > > +description: |

> > > +  On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and MSTP

> > > +  (Module Stop and Software Reset) share the same register block.

> > > +

> > > +  They provide the following functionalities:

> > > +    - The CPG block generates various core clocks,

> > > +    - The MSTP block provides two functions:

> > > +        1. Module Stop, providing a Clock Domain to control the clock supply

> > > +           to individual SoC devices,

> > > +        2. Reset Control, to perform a software reset of individual SoC devices.

> > > +

> > > +properties:

> > > +  compatible:

> > > +    const: renesas,r9a07g044l-cpg  # RZ/G2L

> >

> > renesas,r9a07g044-cpg?

> >

> As some IP blocks present in RZ/G2L aren't present in RZ/G2LC clock

> handling will differ so as a result SoC specific compatible string is

> added.


The RZ/G2L Hardware User's Manual Rev. 0.41 doesn't mention any
differences between the CPG on RZ/G2L and RZ/G2LC.  So I think it's
safe to have a single driver for both members.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
new file mode 100644
index 000000000000..463d6667951b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
@@ -0,0 +1,80 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Renesas RZ/G2L Clock Pulse Generator / Module Stop and Software Reset
+
+maintainers:
+  - Geert Uytterhoeven <geert+renesas@glider.be>
+
+description: |
+  On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and MSTP
+  (Module Stop and Software Reset) share the same register block.
+
+  They provide the following functionalities:
+    - The CPG block generates various core clocks,
+    - The MSTP block provides two functions:
+        1. Module Stop, providing a Clock Domain to control the clock supply
+           to individual SoC devices,
+        2. Reset Control, to perform a software reset of individual SoC devices.
+
+properties:
+  compatible:
+    const: renesas,r9a07g044l-cpg  # RZ/G2L
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: extal
+
+  '#clock-cells':
+    description: |
+      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
+        and a core clock reference, as defined in
+        <dt-bindings/clock/*-cpg-mssr.h>
+      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
+        a module number, as defined in the datasheet.
+    const: 2
+
+  '#power-domain-cells':
+    description:
+      SoC devices that are part of the CPG/MSTP Clock Domain and can be
+      power-managed through Module Stop should refer to the CPG device node
+      in their "power-domains" property, as documented by the generic PM Domain
+      bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
+    const: 0
+
+  '#reset-cells':
+    description:
+      The single reset specifier cell must be the module number, as defined in
+      the datasheet.
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - '#clock-cells'
+  - '#power-domain-cells'
+  - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    cpg: clock-controller@11010000 {
+            compatible = "renesas,r9a07g044l-cpg";
+            reg = <0x11010000 0x10000>;
+            clocks = <&extal_clk>;
+            clock-names = "extal";
+            #clock-cells = <2>;
+            #power-domain-cells = <0>;
+            #reset-cells = <1>;
+    };