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[v2,8/9] MAINTAINERS: riscv: add entry for Bouffalolab SoC

Message ID 20221127132448.4034-9-jszhang@kernel.org
State New
Headers show
Series riscv: add Bouffalolab bl808 support | expand

Commit Message

Jisheng Zhang Nov. 27, 2022, 1:24 p.m. UTC 
Add Jisheng Zhang as Bouffalolab SoC maintainer.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 MAINTAINERS | 9 +++++++++
 1 file changed, 9 insertions(+)
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Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index 00ff4a2949b8..a6b04249853c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17729,6 +17729,15 @@  F:	arch/riscv/
 N:	riscv
 K:	riscv
 
+RISC-V BOUFFALOLAB SOC SUPPORT
+M:	Jisheng Zhang <jszhang@kernel.org>
+L:	linux-riscv@lists.infradead.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/riscv/bouffalolab.yaml
+F:	Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml
+F:	arch/riscv/boot/dts/bouffalolab/
+F:	drivers/tty/serial/bflb_uart.c
+
 RISC-V MICROCHIP FPGA SUPPORT
 M:	Conor Dooley <conor.dooley@microchip.com>
 M:	Daire McNamara <daire.mcnamara@microchip.com>