From patchwork Fri Dec 16 05:26:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kumaravel Thiagarajan X-Patchwork-Id: 634369 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F648C25B04 for ; Thu, 15 Dec 2022 16:52:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230328AbiLOQwx (ORCPT ); Thu, 15 Dec 2022 11:52:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45114 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229985AbiLOQwf (ORCPT ); Thu, 15 Dec 2022 11:52:35 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 316B733C15; Thu, 15 Dec 2022 08:52:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1671123156; x=1702659156; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UknbHQBi9NyGlbtvd4VMO1OEOHNUN4TlCG+0Q6UC2dc=; b=PF36DUvFAG0kfRdK/4Ol9uFkVGV6EfmZlYz2EOaiUZc3uGI5wDnW+uoA AS5Ve//3w+9n21e/AQURp2QmFFFJn7GhajMnNVB1GzVHBfpfEjKotXhib g+/0NsM0k9CN0hQHWiDzgfgGgfdkkl3hRp2IEIFrDQhpPpR/R9Elvnbt5 CiJZwMZGapAcYBkMWMJzA3ZVxwYKjuMbGfopiA2PKJo1nXxGT5jNhOXho Mwdo7iR0vMTpiThOI8FZVG8N/iO9Ifk0K/rR24Uuxs/L+l/hIa+sqR/d1 TDSiFSdFrVh9a+8Qf7Z0NA+9jv19Bc1VehPFClw6Ibk1rZUPs+uAPoaCt g==; X-IronPort-AV: E=Sophos;i="5.96,248,1665471600"; d="scan'208";a="193245139" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 15 Dec 2022 09:52:35 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Thu, 15 Dec 2022 09:52:34 -0700 Received: from CHE-LT-UNGSOFTWARE.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Thu, 15 Dec 2022 09:52:28 -0700 From: Kumaravel Thiagarajan To: CC: , , , , , , , , , , , , , , , , , Tharun Kumar P Subject: [PATCH v9 tty-next 3/4] serial: 8250_pci1xxxx: Add RS485 support to quad-uart driver Date: Fri, 16 Dec 2022 10:56:55 +0530 Message-ID: <20221216052656.2098100-4-kumaravel.thiagarajan@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221216052656.2098100-1-kumaravel.thiagarajan@microchip.com> References: <20221216052656.2098100-1-kumaravel.thiagarajan@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org pci1xxxx uart supports RS485 mode of operation in the hardware with auto-direction control with configurable delay for releasing RTS after the transmission. This patch adds support for the RS485 mode. Co-developed-by: Tharun Kumar P Signed-off-by: Tharun Kumar P Signed-off-by: Kumaravel Thiagarajan Reviewed-by: Ilpo Järvinen --- Changes in v9: - No Change Changes in v8: - Modified datatype of delay_in_baud_periods to u32 Changes in v7: - No Change Changes in v6: - Modified datatype of delay_in_baud_periods to u64 to avoid overflows Changes in v5: - Removed unnecessary assignments - Corrected styling issues in comments Changes in v4: - No Change Changes in v3: - Remove flags sanitization in driver which is taken care in core Changes in v2: - move pci1xxxx_rs485_config to a separate patch with pci1xxxx_rs485_supported. --- drivers/tty/serial/8250/8250_pci1xxxx.c | 50 +++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/drivers/tty/serial/8250/8250_pci1xxxx.c b/drivers/tty/serial/8250/8250_pci1xxxx.c index 325a2d115863..e46c6b835a36 100644 --- a/drivers/tty/serial/8250/8250_pci1xxxx.c +++ b/drivers/tty/serial/8250/8250_pci1xxxx.c @@ -163,6 +163,54 @@ static void pci1xxxx_set_divisor(struct uart_port *port, unsigned int baud, port->membase + UART_BAUD_CLK_DIVISOR_REG); } +static int pci1xxxx_rs485_config(struct uart_port *port, + struct ktermios *termios, + struct serial_rs485 *rs485) +{ + u32 delay_in_baud_periods; + u32 baud_period_in_ns; + u32 mode_cfg = 0; + u32 clock_div; + + /* + * pci1xxxx's uart hardware supports only RTS delay after + * Tx and in units of bit times to a maximum of 15 + */ + if (rs485->flags & SER_RS485_ENABLED) { + mode_cfg = ADCL_CFG_EN | ADCL_CFG_PIN_SEL; + + if (!(rs485->flags & SER_RS485_RTS_ON_SEND)) + mode_cfg |= ADCL_CFG_POL_SEL; + + if (rs485->delay_rts_after_send) { + clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG); + baud_period_in_ns = + FIELD_GET(BAUD_CLOCK_DIV_INT_MSK, clock_div) * + UART_BIT_SAMPLE_CNT; + delay_in_baud_periods = + rs485->delay_rts_after_send * NSEC_PER_MSEC / + baud_period_in_ns; + delay_in_baud_periods = + min_t(u32, delay_in_baud_periods, + FIELD_MAX(ADCL_CFG_RTS_DELAY_MASK)); + mode_cfg |= FIELD_PREP(ADCL_CFG_RTS_DELAY_MASK, + delay_in_baud_periods); + rs485->delay_rts_after_send = + baud_period_in_ns * delay_in_baud_periods / + NSEC_PER_MSEC; + } + } + writel(mode_cfg, port->membase + ADCL_CFG_REG); + return 0; +} + +static const struct serial_rs485 pci1xxxx_rs485_supported = { + .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | + SER_RS485_RTS_AFTER_SEND, + .delay_rts_after_send = 1, + /* Delay RTS before send is not supported */ +}; + static int pci1xxxx_setup(struct pci_dev *pdev, struct uart_8250_port *port, int port_idx) { @@ -173,6 +221,8 @@ static int pci1xxxx_setup(struct pci_dev *pdev, port->port.set_termios = serial8250_do_set_termios; port->port.get_divisor = pci1xxxx_get_divisor; port->port.set_divisor = pci1xxxx_set_divisor; + port->port.rs485_config = pci1xxxx_rs485_config; + port->port.rs485_supported = pci1xxxx_rs485_supported; ret = serial8250_pci_setup_port(pdev, port, 0, port_idx * 256, 0); if (ret < 0)