From patchwork Mon Jul 3 20:15:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 698917 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C6BFC001DD for ; Mon, 3 Jul 2023 20:15:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231446AbjGCUPp (ORCPT ); Mon, 3 Jul 2023 16:15:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231534AbjGCUPn (ORCPT ); Mon, 3 Jul 2023 16:15:43 -0400 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9F1010C3 for ; Mon, 3 Jul 2023 13:15:39 -0700 (PDT) Received: by mail-lf1-x12f.google.com with SMTP id 2adb3069b0e04-4fba86f069bso4310288e87.3 for ; Mon, 03 Jul 2023 13:15:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688415338; x=1691007338; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Dx8H6sR/Wv2lHyyH91PCRRhoBDKfFC/7awuySX6sc+E=; b=YyemVdJZZqqcZbDGfgvusKo2ajz+JVnopYNJiLCRxt2ywCwTrXh+7M/5CbUDdsR0Z8 eVnvoPuTIAePA8vPamG+WnaOTRUH/qn4CIWOGDrFsNz2LZA5HgwGin6GG2QutMWm2Da2 nnTLPtnt6Y07zh+Hf6/iQEJIUWpnuEPs+ajUtN0GGkrmkDAnSgWdUsgivipOhAu0deZs VFYhw+cs7arZbngrfeqBU/ZM4870/rTuO7J6kPTHT/gwqd+l3l99pJDufWTulTZPbZso kilaOQSR27LbGC8cb7PtiWFWGCAhZxkOx41RCV+GUyiO4tTmVdm2dlkrOpvmeby3r/N9 Z4QQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688415338; x=1691007338; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Dx8H6sR/Wv2lHyyH91PCRRhoBDKfFC/7awuySX6sc+E=; b=lT0hPbvUWfnqhx/k6I8asmZPQMtjBX48gKS52mKH5GWz4gr3dIGu3+WARijT8zrkD2 CuigwpUpF++RAc97M4U64xljqyr/VQnt516cDXOLUeiIn4VDZADiZvoi8XhPmnKoswmU K+/lW1PQm59ejikm96ASbV229XGG9qq5QI4wXgm3J9/jEjlFLd6HIleSlzWJc3oSaV/4 IPVzyZdNa46hhG3huo2m8nIMAxQVOs5csRfFU+Q7dJurDkLPiE00rDBvAfNyjoDTmKsk +ZEwurLImr09+LQDdltvEW/Baz0UWdPQZmQ50lyAQhtM777W3rYtaZ+4PCylemKdT94l EW9Q== X-Gm-Message-State: ABy/qLYm/+mOXpUa+wAF867YrWYggDnc5VZkPpMP2QRIn6SJAOSBWXen cic7372vhKf8oVQuTsE/Yqw47A== X-Google-Smtp-Source: APBJJlEq68Mqj65mEs/wSXMg9a5XlDwCIh82LYS0i+587pB9e/O8fA2YMH2Sazury+OS2GI4uEsczA== X-Received: by 2002:ac2:5f43:0:b0:4fb:7675:1c16 with SMTP id 3-20020ac25f43000000b004fb76751c16mr6518599lfz.49.1688415337880; Mon, 03 Jul 2023 13:15:37 -0700 (PDT) Received: from [192.168.1.101] (abyj26.neoplus.adsl.tpnet.pl. [83.9.29.26]) by smtp.gmail.com with ESMTPSA id w27-20020a05651204db00b004fba7edc6cesm1991365lfq.7.2023.07.03.13.15.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jul 2023 13:15:37 -0700 (PDT) From: Konrad Dybcio Date: Mon, 03 Jul 2023 22:15:27 +0200 Subject: [PATCH v2 3/4] interconnect: qcom: sm8250: Fix QUP0 nodes MIME-Version: 1.0 Message-Id: <20230703-topic-8250_qup_icc-v2-3-9ba0a9460be2@linaro.org> References: <20230703-topic-8250_qup_icc-v2-0-9ba0a9460be2@linaro.org> In-Reply-To: <20230703-topic-8250_qup_icc-v2-0-9ba0a9460be2@linaro.org> To: Andy Gross , Bjorn Andersson , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Andi Shyti , Georgi Djakov , Odelu Kukatla , Jonathan Marek , Sibi Sankar Cc: Marijn Suijten , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, linux-i2c@vger.kernel.org, linux-pm@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1688415328; l=5018; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=LIjpAgT5yWqObE8kRNFk8ncn1fTyVzW6dI2ChOcbjrg=; b=4v/po983D07jXh44YYiZvz1jD5J/kLLTGZamo0Q1lccrpxJJ/V5rSB3dAw/fgc6+AANio9T6A SOfqyWfPJjDD/44Q6iKoLQJeOnj7WRiAZBMnP+S4UkcBvYqudZd/VSe X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org The QUP0 BCM relates to some internal property of the QUPs, and should be configured independently of the path to the QUP. In line with other platforms expose QUP_CORE endpoints in order allow this configuration. Fixes: 6df5b349491e ("interconnect: qcom: Add SM8250 interconnect provider driver") Signed-off-by: Konrad Dybcio Reviewed-by: Bjorn Andersson --- drivers/interconnect/qcom/sm8250.c | 74 ++++++++++++++++++++++++++++++++++++-- drivers/interconnect/qcom/sm8250.h | 6 ++++ 2 files changed, 77 insertions(+), 3 deletions(-) diff --git a/drivers/interconnect/qcom/sm8250.c b/drivers/interconnect/qcom/sm8250.c index e3bb008cb219..d3d0196902cd 100644 --- a/drivers/interconnect/qcom/sm8250.c +++ b/drivers/interconnect/qcom/sm8250.c @@ -164,6 +164,54 @@ DEFINE_QNODE(xs_pcie_modem, SM8250_SLAVE_PCIE_2, 1, 8); DEFINE_QNODE(xs_qdss_stm, SM8250_SLAVE_QDSS_STM, 1, 4); DEFINE_QNODE(xs_sys_tcu_cfg, SM8250_SLAVE_TCU, 1, 8); +static struct qcom_icc_node qup0_core_master = { + .name = "qup0_core_master", + .id = SM8250_MASTER_QUP_CORE_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_SLAVE_QUP_CORE_0 }, +}; + +static struct qcom_icc_node qup1_core_master = { + .name = "qup1_core_master", + .id = SM8250_MASTER_QUP_CORE_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_SLAVE_QUP_CORE_1 }, +}; + +static struct qcom_icc_node qup2_core_master = { + .name = "qup2_core_master", + .id = SM8250_MASTER_QUP_CORE_2, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_SLAVE_QUP_CORE_2 }, +}; + +static struct qcom_icc_node qup0_core_slave = { + .name = "qup0_core_slave", + .id = SM8250_SLAVE_QUP_CORE_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup1_core_slave = { + .name = "qup1_core_slave", + .id = SM8250_SLAVE_QUP_CORE_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup2_core_slave = { + .name = "qup2_core_slave", + .id = SM8250_SLAVE_QUP_CORE_2, + .channels = 1, + .buswidth = 4, +}; + DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); @@ -172,7 +220,7 @@ DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1); DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu); DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf); -DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2, &qhm_qup0); +DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup0_core_master, &qup1_core_master, &qup2_core_master); DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc); DEFINE_QBCM(bcm_mm3, "MM3", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp); DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps); @@ -193,7 +241,6 @@ DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gemnoc); DEFINE_QBCM(bcm_sn12, "SN12", false, &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc); static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { - &bcm_qup0, &bcm_sn12, }; @@ -222,10 +269,29 @@ static const struct qcom_icc_desc sm8250_aggre1_noc = { static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { &bcm_ce0, - &bcm_qup0, &bcm_sn12, }; +static struct qcom_icc_bcm * const qup_virt_bcms[] = { + &bcm_qup0, +}; + +static struct qcom_icc_node *qup_virt_nodes[] = { + [MASTER_QUP_CORE_0] = &qup0_core_master, + [MASTER_QUP_CORE_1] = &qup1_core_master, + [MASTER_QUP_CORE_2] = &qup2_core_master, + [SLAVE_QUP_CORE_0] = &qup0_core_slave, + [SLAVE_QUP_CORE_1] = &qup1_core_slave, + [SLAVE_QUP_CORE_2] = &qup2_core_slave, +}; + +static const struct qcom_icc_desc sm8250_qup_virt = { + .nodes = qup_virt_nodes, + .num_nodes = ARRAY_SIZE(qup_virt_nodes), + .bcms = qup_virt_bcms, + .num_bcms = ARRAY_SIZE(qup_virt_bcms), +}; + static struct qcom_icc_node * const aggre2_noc_nodes[] = { [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, [MASTER_QDSS_BAM] = &qhm_qdss_bam, @@ -518,6 +584,8 @@ static const struct of_device_id qnoc_of_match[] = { .data = &sm8250_mmss_noc}, { .compatible = "qcom,sm8250-npu-noc", .data = &sm8250_npu_noc}, + { .compatible = "qcom,sm8250-qup-virt", + .data = &sm8250_qup_virt }, { .compatible = "qcom,sm8250-system-noc", .data = &sm8250_system_noc}, { } diff --git a/drivers/interconnect/qcom/sm8250.h b/drivers/interconnect/qcom/sm8250.h index 209ab195f21f..032665093c5b 100644 --- a/drivers/interconnect/qcom/sm8250.h +++ b/drivers/interconnect/qcom/sm8250.h @@ -158,5 +158,11 @@ #define SM8250_SLAVE_VSENSE_CTRL_CFG 147 #define SM8250_SNOC_CNOC_MAS 148 #define SM8250_SNOC_CNOC_SLV 149 +#define SM8250_MASTER_QUP_CORE_0 150 +#define SM8250_MASTER_QUP_CORE_1 151 +#define SM8250_MASTER_QUP_CORE_2 152 +#define SM8250_SLAVE_QUP_CORE_0 153 +#define SM8250_SLAVE_QUP_CORE_1 154 +#define SM8250_SLAVE_QUP_CORE_2 155 #endif