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This patch adds an UART configuration to capture the hardware capabilities of MUEX50 UART and apply to Moxa PCI serial boards. Signed-off-by: Crescent Hsieh --- drivers/tty/serial/8250/8250_pci.c | 3 +++ drivers/tty/serial/8250/8250_port.c | 8 ++++++++ include/uapi/linux/serial_core.h | 3 +++ 3 files changed, 14 insertions(+) diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c index e2fcddec9ab5..3ccbb406f505 100644 --- a/drivers/tty/serial/8250/8250_pci.c +++ b/drivers/tty/serial/8250/8250_pci.c @@ -2159,6 +2159,9 @@ pci_moxa_setup(struct serial_private *priv, unsigned int bar = FL_GET_BASE(board->flags); int offset; + port->port.flags |= UPF_FIXED_TYPE; + port->port.type = PORT_MUEX50; + if (pci_moxa_is_pcie(dev->device) || pci_moxa_is_mini_pcie(dev->device)) { if (pci_moxa_supported_rs(dev) & MOXA_SUPP_RS485) { port->port.rs485_config = pci_moxa_rs485_config; diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c index 893bc493f662..c3de350e9a30 100644 --- a/drivers/tty/serial/8250/8250_port.c +++ b/drivers/tty/serial/8250/8250_port.c @@ -319,6 +319,14 @@ static const struct serial8250_config uart_config[] = { .rxtrig_bytes = {1, 8, 16, 30}, .flags = UART_CAP_FIFO | UART_CAP_AFE, }, + [PORT_MUEX50] = { + .name = "Moxa PCIe UART", + .fifo_size = 128, + .tx_loadsz = 128, + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, + .rxtrig_bytes = {1, 4, 8, 14}, + .flags = UART_CAP_FIFO, + }, }; /* Uart divisor latch read */ diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h index 9c007a106330..5afeb6d99e7e 100644 --- a/include/uapi/linux/serial_core.h +++ b/include/uapi/linux/serial_core.h @@ -231,6 +231,9 @@ /* Sunplus UART */ #define PORT_SUNPLUS 123 +/* Moxa PCIe UART */ +#define PORT_MUEX50 124 + /* Generic type identifier for ports which type is not important to userspace. */ #define PORT_GENERIC (-1)