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Wysocki" , Praveen Talari , , , , , CC: , , , , , , Subject: [PATCH v2 7/9] serial: qcom-geni: move clock-rate logic to separate function Date: Fri, 18 Apr 2025 20:42:33 +0530 Message-ID: <20250418151235.27787-8-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250418151235.27787-1-quic_ptalari@quicinc.com> References: <20250418151235.27787-1-quic_ptalari@quicinc.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=WecMa1hX c=1 sm=1 tr=0 ts=68026c31 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=XR8D0OoHHMoA:10 a=COk6AnOGAAAA:8 a=X08zvMDfRsL5Z2rP0xYA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: 5A4YgC4uY0PnbUAsFDc3dPb5JlJNLpLj X-Proofpoint-ORIG-GUID: 5A4YgC4uY0PnbUAsFDc3dPb5JlJNLpLj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-18_05,2025-04-17_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 spamscore=0 malwarescore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504180112 Facilitates future modifications within the new function, leading to better readability and maintainability of the code. Move the code that handles the actual logic of clock-rate calculations to a separate function geni_serial_set_rate() which enhances code readability. Signed-off-by: Praveen Talari --- v1 -> v2 - resolved build warnings for datatype format specifiers - removed double spaces in log --- drivers/tty/serial/qcom_geni_serial.c | 62 +++++++++++++++++---------- 1 file changed, 39 insertions(+), 23 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index 2cd2085473f3..60afee3884a6 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -1283,27 +1283,14 @@ static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud, return ser_clk; } -static void qcom_geni_serial_set_termios(struct uart_port *uport, - struct ktermios *termios, - const struct ktermios *old) +static int geni_serial_set_rate(struct uart_port *uport, unsigned long baud) { - unsigned int baud; - u32 bits_per_char; - u32 tx_trans_cfg; - u32 tx_parity_cfg; - u32 rx_trans_cfg; - u32 rx_parity_cfg; - u32 stop_bit_len; - unsigned int clk_div; - u32 ser_clk_cfg; struct qcom_geni_serial_port *port = to_dev_port(uport); unsigned long clk_rate; - u32 ver, sampling_rate; unsigned int avg_bw_core; - unsigned long timeout; - - /* baud rate */ - baud = uart_get_baud_rate(uport, termios, old, 300, 4000000); + unsigned int clk_div; + u32 ver, sampling_rate; + u32 ser_clk_cfg; sampling_rate = UART_OVERSAMPLING; /* Sampling rate is halved for IP versions >= 2.5 */ @@ -1315,13 +1302,13 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport, sampling_rate, &clk_div); if (!clk_rate) { dev_err(port->se.dev, - "Couldn't find suitable clock rate for %u\n", + "Couldn't find suitable clock rate for %lu\n", baud * sampling_rate); - return; + return -EINVAL; } - dev_dbg(port->se.dev, "desired_rate = %u, clk_rate = %lu, clk_div = %u\n", - baud * sampling_rate, clk_rate, clk_div); + dev_dbg(port->se.dev, "desired_rate = %lu, clk_rate = %lu, clk_div = %u\n", + baud * sampling_rate, clk_rate, clk_div); uport->uartclk = clk_rate; port->clk_rate = clk_rate; @@ -1339,6 +1326,37 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport, port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud); geni_icc_set_bw(&port->se); + writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); + writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); + return 0; +} + +static void qcom_geni_serial_set_termios(struct uart_port *uport, + struct ktermios *termios, + const struct ktermios *old) +{ + struct qcom_geni_serial_port *port = to_dev_port(uport); + unsigned int baud; + unsigned long timeout; + u32 bits_per_char; + u32 tx_trans_cfg; + u32 tx_parity_cfg; + u32 rx_trans_cfg; + u32 rx_parity_cfg; + u32 stop_bit_len; + int ret = 0; + + /* baud rate */ + baud = uart_get_baud_rate(uport, termios, old, 300, 4000000); + + ret = geni_serial_set_rate(uport, baud); + if (ret) { + dev_err(port->se.dev, + "%s: Failed to set baud:%u ret:%d\n", + __func__, baud, ret); + return; + } + /* parity */ tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG); tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG); @@ -1406,8 +1424,6 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport, writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); - writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); - writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); } #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE