[v10,01/10] dt-bindings: serial: Added secondary clock for RZ/T2H RSCI

At boot, the default clock is the PCLKM core clock (synchronous
clock, which is enabled by the bootloader).
For different baudrates, the asynchronous clock input must be used.
Clock selection is made by an internal register of RCSI.

Add the optional "sck", external clock input.

Also remove the unneeded serial0 alias from the dts example.

Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
---
Changes v9->v10:
 - mention sck in description
 - no maxItems on clock-names
 - fixed the #include dependency in dts example
Changes v8->v9:
 - typo in description
 - named clocks 'operational' and 'bus', and added optional 'sck' clock
 - uses value of 2nd core clock in example to break the dependency on cpg patch
---
 .../bindings/serial/renesas,rsci.yaml           | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

On Fri, May 23, 2025 at 04:24:05PM +0200, Thierry Bultel wrote:
> At boot, the default clock is the PCLKM core clock (synchronous
> clock, which is enabled by the bootloader).
> For different baudrates, the asynchronous clock input must be used.
> Clock selection is made by an internal register of RCSI.
> 
> Add the optional "sck", external clock input.
> 
> Also remove the unneeded serial0 alias from the dts example.
> 
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> ---
> Changes v9->v10:
>  - mention sck in description
>  - no maxItems on clock-names
>  - fixed the #include dependency in dts example
> Changes v8->v9:
>  - typo in description
>  - named clocks 'operational' and 'bus', and added optional 'sck' clock
>  - uses value of 2nd core clock in example to break the dependency on cpg patch
> ---
>  .../bindings/serial/renesas,rsci.yaml           | 17 +++++++++--------
>  1 file changed, 9 insertions(+), 8 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> index ea879db5f485..1bf255407df0 100644
> --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> @@ -35,10 +35,15 @@ properties:
>        - const: tei
>  
>    clocks:
> -    maxItems: 1
> +    minItems: 2
> +    maxItems: 3
>  
>    clock-names:
> -    const: fck # UART functional clock
> +    minItems: 2
> +    items:
> +      - const: operation
> +      - const: bus
> +      - const: sck # optional external clock input

You can't just change the clock names. What happens to users of 'fck'?

And you can't make additional entries required. What happens to users 
with only 1 clock defined?

Rob

Hi Rob,

On Thu, 5 Jun 2025 at 16:39, Rob Herring <robh@kernel.org> wrote:
> On Fri, May 23, 2025 at 04:24:05PM +0200, Thierry Bultel wrote:
> > At boot, the default clock is the PCLKM core clock (synchronous
> > clock, which is enabled by the bootloader).
> > For different baudrates, the asynchronous clock input must be used.
> > Clock selection is made by an internal register of RCSI.
> >
> > Add the optional "sck", external clock input.
> >
> > Also remove the unneeded serial0 alias from the dts example.
> >
> > Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> > ---
> > Changes v9->v10:
> >  - mention sck in description
> >  - no maxItems on clock-names
> >  - fixed the #include dependency in dts example
> > Changes v8->v9:
> >  - typo in description
> >  - named clocks 'operational' and 'bus', and added optional 'sck' clock
> >  - uses value of 2nd core clock in example to break the dependency on cpg patch
> > ---
> >  .../bindings/serial/renesas,rsci.yaml           | 17 +++++++++--------
> >  1 file changed, 9 insertions(+), 8 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > index ea879db5f485..1bf255407df0 100644
> > --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > @@ -35,10 +35,15 @@ properties:
> >        - const: tei
> >
> >    clocks:
> > -    maxItems: 1
> > +    minItems: 2
> > +    maxItems: 3
> >
> >    clock-names:
> > -    const: fck # UART functional clock
> > +    minItems: 2
> > +    items:
> > +      - const: operation
> > +      - const: bus
> > +      - const: sck # optional external clock input
>
> You can't just change the clock names. What happens to users of 'fck'?
>
> And you can't make additional entries required. What happens to users
> with only 1 clock defined?

There are no users of the bindings yet, and the RSCI driver updates haven't
reached linux-next yet.

Gr{oetje,eeting}s,

                        Geert