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[0/2] Driver for Cadence xSPI flash controller

Message ID 1607500678-23862-1-git-send-email-jpawar@cadence.com
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Series Driver for Cadence xSPI flash controller | expand

Message

Jayshri Pawar Dec. 9, 2020, 7:57 a.m. UTC 
Command processing
Driver uses STIG work mode to communicate with flash memories.
In this mode, controller sends low-level instructions to memory.
Each instruction is 128-bit width. There is special instruction
DataSequence which carries information about data phase.
Driver uses Slave DMA interface to transfer data as only this
interface can be used in STIG work mode.

PHY initialization
The initialization of PHY module in Cadence XSPI controller
is done by driving external pin-strap signals to controller.
Next, driver runs PHY training to find optimal value of
read_dqs_delay parameter. Controller checks device discovery
status and if it's completed and with no error PHY training
passes.

Jayshri Pawar (2):
  Add support for Cadence XSPI controller
  Add dt-bindings documentation for Cadence XSPI controller

 .../devicetree/bindings/spi/cdns,xspi.yaml         | 164 ++++
 drivers/spi/Kconfig                                |  11 +
 drivers/spi/Makefile                               |   1 +
 drivers/spi/spi-cadence-xspi.c                     | 894 +++++++++++++++++++++
 4 files changed, 1070 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/spi/cdns,xspi.yaml
 create mode 100644 drivers/spi/spi-cadence-xspi.c