mbox series

[v9,0/5] spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC

Message ID 20201124041840.31066-1-vadivel.muruganx.ramuthevar@linux.intel.com
Headers show
Series spi: cadence-quadspi: Add QSPI controller support for Intel LGM SoC | expand

Message

Ramuthevar,Vadivel MuruganX Nov. 24, 2020, 4:18 a.m. UTC
Add QSPI controller support for Intel LGM SoC. 

Patches to move move bindings over to
"Documentation/devicetree/bindings/spi/" directory and also added compatible
Support for Intel platform.

dt-bindings: spi: cadence-qspi: Add support for Intel lgm-qspi
(earlier patch mail thread and Ack-by)
link: "https://lore.kernel.org/lkml/5d6d1b85.1c69fb81.96938.0315@mx.google.com/"

Reference:
        https://lkml.org/lkml/2020/6/1/50
---
v9:
  - Vignesh review comments address and update
  - Retain the patchv4 move the binding documentation from mtd to spi
    directory.
  - Add intel's compatible string over the legacy documentation
  - Remove unused variable, CQSPI_SUPPORTS_MULTI_CHIPSELECT macro and check  
  - YAML convertion patch alone dropped
v8:
  - As Mark suggested to add the dt-bindings documentation patches
    end of the series , so dropped.
v7:
  - Rob's review comments address and fixed dt-schema warning
  - Pratyush review comments address and update
  - DAC bit reset to 0 and 1 (enable/disable)
  - tested QSI-NOR flash mx25l12805d on LGM soc, it's working after disable DAC
  - Linus suggested to use 'num-cs' prperty instead of 'num-chipselect'
v6:
  - Rob's review comments update
  - add compatible string in properly aligned
  - remove cadence-qspi extra comaptible string in example
v5:
  - Rob's review comments update
  - const with single compatible string kept
v4:
  - Rob's review comments update
  - remove '|' no formatting to preserve
  - child node attributes follows under 'properties' under '@[0-9a-f]+$'.
v3:
  - Pratyush review comments update
  - CQSPI_SUPPORTS_MULTI_CHIPSELECT macro used instead of cqspi->use_direct_mode
  - disable DAC support placed in end of controller_init
v2:
  - Rob's review comments update for dt-bindings
  - add 'oneOf' for compatible selection
  - drop un-neccessary descriptions
  - add the cdns,is-decoded-cs and cdns,rclk-en properties as schema
  - remove 'allOf' in not required place
  - add AdditionalProperties false
  - add minItems/maxItems for qspi reset attributes

resend-v1:
  - As per Mark's suggestion , reorder the patch series 1-3 driver
    support patches, series 4-6 dt-bindings patches.
v1:
  - initial version

Ramuthevar Vadivel Murugan (5):
  spi: cadence-quadspi: Add QSPI support for Intel LGM SoC
  spi: cadence-quadspi: Disable the DAC for Intel LGM SoC
  spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC
  spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi
  dt-bindings: spi: cadence-qspi: Add support for Intel lgm-qspi

 .../bindings/{mtd => spi}/cadence-quadspi.txt      |  1 +
 drivers/spi/Kconfig                                |  2 +-
 drivers/spi/spi-cadence-quadspi.c                  | 24 ++++++++++++++++++----
 3 files changed, 22 insertions(+), 5 deletions(-)
 rename Documentation/devicetree/bindings/{mtd => spi}/cadence-quadspi.txt (97%)

Comments

Kim, Cheol Yong Jan. 14, 2021, 3:35 a.m. UTC | #1
On 1/13/2021 11:28 PM, Mark Brown wrote:
> On Tue, 24 Nov 2020 12:18:35 +0800, Ramuthevar, Vadivel MuruganX wrote:
>> Add QSPI controller support for Intel LGM SoC.
>>
>> Patches to move move bindings over to
>> "Documentation/devicetree/bindings/spi/" directory and also added compatible
>> Support for Intel platform.
>>
>> dt-bindings: spi: cadence-qspi: Add support for Intel lgm-qspi
>> (earlier patch mail thread and Ack-by)
>> link: "https://lore.kernel.org/lkml/5d6d1b85.1c69fb81.96938.0315@mx.google.com/"
>>
>> [...]
> Applied to
>
>     https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
>
> Thanks!
>
> [1/5] spi: cadence-quadspi: Add QSPI support for Intel LGM SoC
>        commit: ab2d28750aacb773dc42d72fbad59146e8a6db5e
> [2/5] spi: cadence-quadspi: Disable the DAC for Intel LGM SoC
>        commit: ad2775dc3fc5d30dd51984ccbaa736cc7ea9caca
> [3/5] spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC
>        commit: b436fb7d29bfa48ff5e00cbf413609c7a6d4d81e
> [4/5] spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi
>        commit: eb4aadc31ef4224b926d5165048cb297f4bda34f
> [5/5] dt-bindings: spi: cadence-qspi: Add support for Intel lgm-qspi
>        commit: fcebca39938fa9f6ed03f27fc75645ad7fd489e9
>
> All being well this means that it will be integrated into the linux-next
> tree (usually sometime in the next 24 hours) and sent to Linus during
> the next merge window (or sooner if it is a bug fix), however if
> problems are discovered then the patch may be dropped or reverted.
>
> You may get further e-mails resulting from automated or manual testing
> and review of the tree, please engage with people reporting problems and
> send followup patches addressing any issues that are reported if needed.
>
> If any updates are required or you are submitting further changes they
> should be sent as incremental updates against current git, existing
> patches will not be replaced.
>
> Please add any relevant lists and maintainers to the CCs when replying
> to this mail.

Thanks Mark!

Vadivel left company. Added Rahul <rtanwar@maxlinear.com> as a maintainer


>
> Thanks,
> Mark