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[0/4] spi: axi-spi-engine: offload instruction optimization

Message ID 20250428-adi-main-v1-0-4b8a1b88a212@baylibre.com
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Series spi: axi-spi-engine: offload instruction optimization | expand

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David Lechner April 28, 2025, 8:58 p.m. UTC 
In order to achieve a 4 MSPS rate on a 16-bit ADC with a 80 MHz SCLK
using the SPI offload feature of the AXI SPI Engine, we need to shave
off some time that is spent executing unnecessary instructions. There
are a few one-time setup instructions that can be moved so that they
execute only once when the SPI offload trigger is enabled rather than
repeating each time the offload is triggered. Additionally, a recent
change to the IP block allows dropping the SYNC instruction completely.
With these changes, we are left with only the 3 instructions that are
needed to to assert CS, transfer the data, and deassert CS. This makes
3 + 16 * 12.5 ns = 237.5 ns < 250 ns which is comfortably within the
available time period.

Signed-off-by: David Lechner <dlechner@baylibre.com>
---
David Lechner (4):
      spi: axi-spi-engine: wait for completion in setup
      spi: axi-spi-engine: don't repeat mode config for offload
      spi: axi-spi-engine: optimize bits_per_word for offload
      spi: axi-spi-engine: omit SYNC from offload instructions

 drivers/spi/spi-axi-spi-engine.c | 91 +++++++++++++++++++++++++++++++++++++---
 1 file changed, 85 insertions(+), 6 deletions(-)
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base-commit: aba9c2fee9598d797034ffd289b0da770d9119e8
change-id: 20250331-adi-main-46863acfc540

Best regards,