[next,0/2] spi: spi-qpic-snand: enable 8 bits ECC strength support

Message ID	20250502-qpic-snand-8bit-ecc-v1-0-95f3cd08bbc5@gmail.com
Headers	show Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D8742DC78C; Fri, 2 May 2025 19:31:35 +0000 (UTC) From: Gabor Juhos <j4g8y7@gmail.com> Subject: [PATCH next 0/2] spi: spi-qpic-snand: enable 8 bits ECC strength support Date: Fri, 02 May 2025 21:31:15 +0200 Message-Id: <20250502-qpic-snand-8bit-ecc-v1-0-95f3cd08bbc5@gmail.com> Precedence: bulk MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: Mark Brown <broonie@kernel.org>, Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>, Miquel Raynal <miquel.raynal@bootlin.com>, Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com> Cc: Varadarajan Narayanan <quic_varada@quicinc.com>, Md Sadre Alam <quic_mdalam@quicinc.com>, Sricharan Ramabadhran <quic_srichara@quicinc.com>, linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Gabor Juhos <j4g8y7@gmail.com>
Series	spi: spi-qpic-snand: enable 8 bits ECC strength support \| expand [next,0/2] spi: spi-qpic-snand: enable 8 bits ECC strength support [next,1/2] mtd: nand: qpic-common: add defines for ECC_MODE values [next,2/2] spi: spi-qpic-snand: add support for 8 bits ECC strength

Message ID

20250502-qpic-snand-8bit-ecc-v1-0-95f3cd08bbc5@gmail.com

Headers

From: Gabor Juhos <j4g8y7@gmail.com>
Subject: [PATCH next 0/2] spi: spi-qpic-snand: enable 8 bits ECC strength
 support
Date: Fri, 02 May 2025 21:31:15 +0200
Message-Id: <20250502-qpic-snand-8bit-ecc-v1-0-95f3cd08bbc5@gmail.com>
Precedence: bulk
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: 7bit
To: Mark Brown <broonie@kernel.org>,
 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
 Miquel Raynal <miquel.raynal@bootlin.com>,
 Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>
Cc: Varadarajan Narayanan <quic_varada@quicinc.com>,
 Md Sadre Alam <quic_mdalam@quicinc.com>,
 Sricharan Ramabadhran <quic_srichara@quicinc.com>,
 linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org,
 linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
 Gabor Juhos <j4g8y7@gmail.com>

Series

spi: spi-qpic-snand: enable 8 bits ECC strength support | expand

Message

Gabor Juhos May 2, 2025, 7:31 p.m. UTC

This small patch set adds support for 8 bits ECC strength, which widens
the range of the usable SPI NAND chips with the driver.

The series should be integrated via the SPI tree, as that contains
prerequisite changes.

Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
---
Gabor Juhos (2):
      mtd: nand: qpic-common: add defines for ECC_MODE values
      spi: spi-qpic-snand: add support for 8 bits ECC strength

 drivers/mtd/nand/raw/qcom_nandc.c    |  6 +++---
 drivers/spi/spi-qpic-snand.c         | 21 ++++++++++++++++-----
 include/linux/mtd/nand-qpic-common.h |  2 ++
 3 files changed, 21 insertions(+), 8 deletions(-)
---
base-commit: 39d6783f6488786301f36b0e7c619f220c3e8d2c
change-id: 20250208-qpic-snand-8bit-ecc-dc804fd08592
prerequisite-change-id: 20250320-qpic-snand-kmalloc-3f6c1fb6c873:v1
prerequisite-patch-id: ec9e9786ca59fcddf9502d0ba5b0f4e6593aab62
prerequisite-change-id: 20250501-qpic-snand-validate-ecc-383b3e33e238:v1
prerequisite-patch-id: 7a549e08b3075d20c5014bb3d2151643aa956f5c

Best regards,