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Tue, 29 Jun 2021 16:39:00 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; kernel.org; dkim=none (message not signed) header.d=none; kernel.org; dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT027.mail.protection.outlook.com (10.13.172.205) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4264.18 via Frontend Transport; Tue, 29 Jun 2021 16:39:00 +0000 Received: from jatayu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.4; Tue, 29 Jun 2021 11:38:57 -0500 From: Nehal Bakulchandra Shah To: CC: , , "Nehal Bakulchandra Shah" , Shyam Sundar S K , Liang Liang Subject: [RESEND PATCH v2 2/2] spi:amd: Fix for transfer large size of data Date: Tue, 29 Jun 2021 22:08:34 +0530 Message-ID: <20210629163834.581774-3-Nehal-Bakulchandra.shah@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210629163834.581774-1-Nehal-Bakulchandra.shah@amd.com> References: <20210629163834.581774-1-Nehal-Bakulchandra.shah@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6f4199b9-ffdc-4fc9-0d5d-08d93b1c65e3 X-MS-TrafficTypeDiagnostic: DM5PR12MB1803: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3968; 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SFS:(4636009)(136003)(39860400002)(346002)(376002)(396003)(36840700001)(46966006)(1076003)(26005)(82740400003)(186003)(16526019)(6666004)(82310400003)(83380400001)(7696005)(47076005)(86362001)(356005)(81166007)(4326008)(70206006)(70586007)(54906003)(2616005)(5660300002)(316002)(36860700001)(336012)(36756003)(8676002)(8936002)(2906002)(426003)(6916009)(478600001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jun 2021 16:39:00.3058 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6f4199b9-ffdc-4fc9-0d5d-08d93b1c65e3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT027.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1803 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Hardware has 72 bytes of FIFO.This patch addresses the same by means of software workaround. Reviewed-by: Shyam Sundar S K Reviewed-by: Liang Liang Signed-off-by: Nehal Bakulchandra Shah --- drivers/spi/spi-amd.c | 77 ++++++++++++++++++++++++++++++++++--------- 1 file changed, 62 insertions(+), 15 deletions(-) diff --git a/drivers/spi/spi-amd.c b/drivers/spi/spi-amd.c index e65e7178d5fe..d608c27fe599 100644 --- a/drivers/spi/spi-amd.c +++ b/drivers/spi/spi-amd.c @@ -2,9 +2,10 @@ // // AMD SPI controller driver // -// Copyright (c) 2020, Advanced Micro Devices, Inc. +// Copyright (c) 2020-2021, Advanced Micro Devices, Inc. // -// Author: Sanjay R Mehta +// Authors: Sanjay R Mehta +// Nehal Bakulchandra Shah #include #include @@ -29,7 +30,7 @@ #define AMD_SPI_TX_COUNT_REG 0x48 #define AMD_SPI_RX_COUNT_REG 0x4B #define AMD_SPI_STATUS_REG 0x4C - +#define AMD_SPI_FIFO_SIZE 72 #define AMD_SPI_MEM_SIZE 200 /* M_CMD OP codes for SPI */ @@ -215,8 +216,8 @@ static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi, u8 cmd_opcode; u8 *buf = NULL; u32 m_cmd = 0; - u32 i = 0; - u32 tx_len = 0, rx_len = 0; + u32 i = 0, it = 0, tx_index = 0, rx_index = 0; + u32 tx_len = 0, rx_len = 0, iters = 0, remaining = 0; list_for_each_entry(xfer, &message->transfers, transfer_list) { @@ -230,17 +231,40 @@ static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi, tx_len = xfer->len - 1; cmd_opcode = *(u8 *)xfer->tx_buf; buf++; + + tx_index = 0; + iters = tx_len / AMD_SPI_FIFO_SIZE; + remaining = tx_len % AMD_SPI_FIFO_SIZE; + + for (it = 0; it < iters; it++) { + amd_spi_clear_fifo_ptr(master); + amd_spi_set_opcode(master, cmd_opcode); + + amd_spi_set_tx_count(master, AMD_SPI_FIFO_SIZE); + /* Write data into the FIFO. */ + for (i = 0; i < AMD_SPI_FIFO_SIZE; i++) { + iowrite8(buf[tx_index], + ((u8 __iomem *)amd_spi->io_remap_addr + + AMD_SPI_FIFO_BASE + i)); + tx_index++; + } + + /* Execute command */ + amd_spi_execute_opcode(master); + } + + amd_spi_clear_fifo_ptr(master); amd_spi_set_opcode(master, cmd_opcode); + amd_spi_set_tx_count(master, remaining); /* Write data into the FIFO. */ - for (i = 0; i < tx_len; i++) { - iowrite8(buf[i], + for (i = 0; i < remaining; i++) { + iowrite8(buf[tx_index], ((u8 __iomem *)amd_spi->io_remap_addr + - AMD_SPI_FIFO_BASE + i)); + AMD_SPI_FIFO_BASE + i)); + tx_index++; } - amd_spi_set_tx_count(master, tx_len); - amd_spi_clear_fifo_ptr(master); /* Execute command */ amd_spi_execute_opcode(master); } @@ -250,16 +274,38 @@ static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi, * FIFO */ rx_len = xfer->len; + rx_index = 0; + iters = rx_len / AMD_SPI_FIFO_SIZE; + remaining = rx_len % AMD_SPI_FIFO_SIZE; buf = (u8 *)xfer->rx_buf; - amd_spi_set_rx_count(master, rx_len); + + for (it = 0 ; it < iters; it++) { + amd_spi_clear_fifo_ptr(master); + + amd_spi_set_rx_count(master, AMD_SPI_FIFO_SIZE); + + /* Execute command */ + amd_spi_execute_opcode(master); + /* Read data from FIFO to receive buffer */ + for (i = 0; i < AMD_SPI_FIFO_SIZE; i++) { + buf[rx_index] = amd_spi_readreg8(master, AMD_SPI_FIFO_BASE + + tx_len + i); + rx_index++; + } + } + amd_spi_clear_fifo_ptr(master); + + amd_spi_set_rx_count(master, remaining); + /* Execute command */ amd_spi_execute_opcode(master); /* Read data from FIFO to receive buffer */ - for (i = 0; i < rx_len; i++) - buf[i] = amd_spi_readreg8(master, - AMD_SPI_FIFO_BASE + - tx_len + i); + for (i = 0; i < remaining; i++) { + buf[rx_index] = amd_spi_readreg8(master, AMD_SPI_FIFO_BASE + + tx_len + i); + rx_index++; + } } } @@ -365,4 +411,5 @@ module_platform_driver(amd_spi_driver); MODULE_LICENSE("Dual BSD/GPL"); MODULE_AUTHOR("Sanjay Mehta "); +MODULE_AUTHOR("Nehal Bakulchandra Shah "); MODULE_DESCRIPTION("AMD SPI Master Controller Driver");