From patchwork Sun Apr 3 13:14:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chuanhong Guo X-Patchwork-Id: 556154 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E25DC4332F for ; Sun, 3 Apr 2022 13:16:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358807AbiDCNSa (ORCPT ); Sun, 3 Apr 2022 09:18:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44688 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358805AbiDCNRr (ORCPT ); Sun, 3 Apr 2022 09:17:47 -0400 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC735E54; Sun, 3 Apr 2022 06:15:53 -0700 (PDT) Received: by mail-pl1-x629.google.com with SMTP id y6so6138921plg.2; Sun, 03 Apr 2022 06:15:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/KKxa3qfvCVRnTRZ4freu2hqQtZPY0z6h6IaQVcQg/k=; b=m/vENM9lvhogRoIDlbupYgq5rx0p0TaAeNuLAb4TO7miAG2u+gYAWrM0TdgdKKH4wW CjOo2kI3Hh3/B1zKZri9bq7YmKARrXX+Ns7NDHfrOuRkluAzL7G2J3SkJcm01NS9QhuS lVv2KOITKHKEGckXA+DkfR5Oh1L4vrRTDWrqWF2j9WySVKHZvv/z8hiCz/oFufZn2Fet OinBXy5286a0MW++V4c+++x+CGX8V5vy7+Ng+6XlydVquBCsc+DNJVhYJ60WjYUtxBC/ 7g+Y4AJi+OU5ljLKfHEO4cBWCrdufx6a0te3MXj2HP5j61wLClEWHEVAT0atyDv4npGW fVXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/KKxa3qfvCVRnTRZ4freu2hqQtZPY0z6h6IaQVcQg/k=; b=rOErjhnDQuNiI/s56SCtgpvU7czvD94dEm4dlBJJv0M8nxI5NQhdpyhafB1DGqNeBA gpYvZW0KIqLVb5p/oPIQHGwDCh1ivXLqetXngCHEJxmDNs75DZqhbQgQRXxWL8fbRLpP ceWCOPcOGMhdMoESprVcpCIiTfJqZZsTMeEniEFus9zIUN/hJOtRKY9To53wNYFPQvYj yJQemyuQtpAAbuvkiyrLXYAN9tpLRCAddgznMqQnJ7jHzwlleEYlL4AtcvC0Lv2OUhTN 5TLp86P9YaQ5vcwwmV4XXhoTr32c52BZZ6Aa15IUcKrz5dmnX2q9oJTF4WZG9tTOjFr8 lnSg== X-Gm-Message-State: AOAM53241wlQ28noryGvU2QIZ4hhO3ep+f+XkOHpbbu8nYNsc9JvLGFY cmtBjznieXPE8MQx4oEefZejH82XSFaFj8zJMnQ= X-Google-Smtp-Source: ABdhPJxXGMDGVeqCKGOYjvMF3Px/SiCfGZsXLdIYstyqOWgeLYeNgR12ds/8r8Dq4tb3lQ8nGLb7og== X-Received: by 2002:a17:90a:af86:b0:1c7:db8e:8589 with SMTP id w6-20020a17090aaf8600b001c7db8e8589mr21369924pjq.94.1648991753046; Sun, 03 Apr 2022 06:15:53 -0700 (PDT) Received: from guoguo-omen.lan ([2001:250:3000:7000:7978:d40d:86ff:591d]) by smtp.gmail.com with ESMTPSA id w19-20020a056a0014d300b004fae5e3970csm9272416pfu.35.2022.04.03.06.15.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Apr 2022 06:15:52 -0700 (PDT) From: Chuanhong Guo To: linux-spi@vger.kernel.org Cc: Chuanhong Guo , Mark Brown , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Roger Quadros , Thomas Bogendoerfer , Cai Huoqing , Florian Fainelli , Colin Ian King , Wolfram Sang , Paul Cercueil , Pratyush Yadav , Yu Kuai , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-kernel@vger.kernel.org (open list), linux-mtd@lists.infradead.org (open list:NAND FLASH SUBSYSTEM) Subject: [PATCH resend 3/4] dt-bindings: spi: add binding doc for spi-mtk-snfi Date: Sun, 3 Apr 2022 21:14:52 +0800 Message-Id: <20220403131453.1269229-4-gch981213@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220403131453.1269229-1-gch981213@gmail.com> References: <20220403131453.1269229-1-gch981213@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Add device-tree binding documentation for Mediatek SPI-NAND Flash Interface. Signed-off-by: Chuanhong Guo --- .../bindings/spi/mediatek,spi-mtk-snfi.yaml | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml new file mode 100644 index 000000000000..166c6b50b9d1 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-snfi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SPI-NAND flash controller for MediaTek ARM SoCs + +maintainers: + - Chuanhong Guo + +description: | + The Mediatek SPI-NAND flash controller is an extended version of + the Mediatek NAND flash controller. It can perform standard SPI + instructions with one continuous write and one read for up-to 0xa0 + bytes. It also supports typical SPI-NAND page cache operations + in single, dual or quad IO mode with piplined ECC encoding/decoding + using the accompanying ECC engine. There should be only one spi + slave device following generic spi bindings. + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + enum: + - mediatek,mt7622-snand + - mediatek,mt7629-snand + reg: + items: + - description: core registers + + interrupts: + items: + - description: NFI interrupt + + clocks: + items: + - description: clock used for the controller + - description: clock used for the SPI bus + + clock-names: + items: + - const: nfi_clk + - const: pad_clk + + ecc-engine: + description: device-tree node of the accompanying ECC engine. + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - ecc-engine + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + snfi: spi@1100d000 { + compatible = "mediatek,mt7622-snand"; + reg = <0 0x1100d000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>; + clock-names = "nfi_clk", "pad_clk"; + ecc-engine = <&bch>; + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + nand-ecc-engine = <&snfi>; + }; + }; + };