From patchwork Mon May 9 17:56:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 571182 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8BEEC433FE for ; Mon, 9 May 2022 17:57:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239962AbiEISBe (ORCPT ); Mon, 9 May 2022 14:01:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52264 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239961AbiEISBc (ORCPT ); Mon, 9 May 2022 14:01:32 -0400 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F6111EAF0B; Mon, 9 May 2022 10:57:32 -0700 (PDT) Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4KxpmB64sVz4ySW; Tue, 10 May 2022 03:57:30 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4Kxpm53q4Tz4xcY; Tue, 10 May 2022 03:57:25 +1000 (AEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org Cc: Mark Brown , Tudor Ambarus , Pratyush Yadav , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , linux-aspeed@lists.ozlabs.org, Joel Stanley , Andrew Jeffery , Chin-Ting Kuo , devicetree@vger.kernel.org, Rob Herring , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Tao Ren , =?utf-8?q?C?= =?utf-8?q?=C3=A9dric_Le_Goater?= , Jae Hyun Yoo Subject: [PATCH v7 10/11] ARM: dts: aspeed-g4: Set spi-max-frequency for all flashes Date: Mon, 9 May 2022 19:56:15 +0200 Message-Id: <20220509175616.1089346-11-clg@kaod.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220509175616.1089346-1-clg@kaod.org> References: <20220509175616.1089346-1-clg@kaod.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Tao Ren Set "spi-max-frequency" to 50 MHz for all the flashes under the FMC controller to ensure the clock frequency is calculated correctly. Suggested-by: Cédric Le Goater Tested-by: Jae Hyun Yoo Signed-off-by: Tao Ren Signed-off-by: Cédric Le Goater --- arch/arm/boot/dts/aspeed-g4.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 1c6354cec9f2..530491ae5eb2 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -72,24 +72,28 @@ flash@1 { reg = < 1 >; compatible = "jedec,spi-nor"; spi-rx-bus-width = <2>; + spi-max-frequency = <50000000>; status = "disabled"; }; flash@2 { reg = < 2 >; compatible = "jedec,spi-nor"; spi-rx-bus-width = <2>; + spi-max-frequency = <50000000>; status = "disabled"; }; flash@3 { reg = < 3 >; compatible = "jedec,spi-nor"; spi-rx-bus-width = <2>; + spi-max-frequency = <50000000>; status = "disabled"; }; flash@4 { reg = < 4 >; compatible = "jedec,spi-nor"; spi-rx-bus-width = <2>; + spi-max-frequency = <50000000>; status = "disabled"; }; };