| Message ID | 20220802175755.6530-8-sudip.mukherjee@sifive.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for enhanced SPI for Designware SPI controllers | expand |
On Tue, Aug 02, 2022 at 06:57:51PM +0100, Sudip Mukherjee wrote: > If the transfer of Transmit only mode is using dual/quad/octal SPI then > NDF needs to be updated with the number of data frames. > If the Transmit FIFO goes empty in-between, DWC_ssi masks the serial > clock and wait for rest of the data until the programmed amount of > frames are transferred successfully. > > Signed-off-by: Sudip Mukherjee <sudip.mukherjee@sifive.com> > --- > drivers/spi/spi-dw-core.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c > index 9d499bdf2ce6..8cb30540ad5b 100644 > --- a/drivers/spi/spi-dw-core.c > +++ b/drivers/spi/spi-dw-core.c > @@ -344,7 +344,9 @@ void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi, > dw_writel(dws, DW_SPI_CTRLR0, cr0); > > if (cfg->tmode == DW_SPI_CTRLR0_TMOD_EPROMREAD || > - cfg->tmode == DW_SPI_CTRLR0_TMOD_RO) > + cfg->tmode == DW_SPI_CTRLR0_TMOD_RO || > + (cfg->tmode == DW_SPI_CTRLR0_TMOD_TO && > + (dws->caps & DW_SPI_CAP_EXT_SPI) && cfg->spi_frf)) just (cfg->spi_frf != DW_SPI_CTRLR0_SPI_FRF_STD_SPI && cfg->tmode == DW_SPI_CTRLR0_TMOD_TO) > dw_writel(dws, DW_SPI_CTRLR1, cfg->ndf ? cfg->ndf - 1 : 0); > > /* Note DW APB SSI clock divider doesn't support odd numbers */ > @@ -760,6 +762,8 @@ static int dw_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) > cfg.ndf = op->data.nbytes; > } else { > cfg.tmode = DW_SPI_CTRLR0_TMOD_TO; > + if (enhanced_spi) > + cfg.ndf = op->data.nbytes; This shall be moved to the Enhanced SPI-specific mem-op execution method: dw_spi_exec_enh_mem_op(). -Sergey > } > > dw_spi_enable_chip(dws, 0); > -- > 2.30.2 >
diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 9d499bdf2ce6..8cb30540ad5b 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -344,7 +344,9 @@ void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi, dw_writel(dws, DW_SPI_CTRLR0, cr0); if (cfg->tmode == DW_SPI_CTRLR0_TMOD_EPROMREAD || - cfg->tmode == DW_SPI_CTRLR0_TMOD_RO) + cfg->tmode == DW_SPI_CTRLR0_TMOD_RO || + (cfg->tmode == DW_SPI_CTRLR0_TMOD_TO && + (dws->caps & DW_SPI_CAP_EXT_SPI) && cfg->spi_frf)) dw_writel(dws, DW_SPI_CTRLR1, cfg->ndf ? cfg->ndf - 1 : 0); /* Note DW APB SSI clock divider doesn't support odd numbers */ @@ -760,6 +762,8 @@ static int dw_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) cfg.ndf = op->data.nbytes; } else { cfg.tmode = DW_SPI_CTRLR0_TMOD_TO; + if (enhanced_spi) + cfg.ndf = op->data.nbytes; } dw_spi_enable_chip(dws, 0);
If the transfer of Transmit only mode is using dual/quad/octal SPI then NDF needs to be updated with the number of data frames. If the Transmit FIFO goes empty in-between, DWC_ssi masks the serial clock and wait for rest of the data until the programmed amount of frames are transferred successfully. Signed-off-by: Sudip Mukherjee <sudip.mukherjee@sifive.com> --- drivers/spi/spi-dw-core.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)