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Sat, 18 Mar 2023 22:24:23 +0000 From: Kevin Groeneveld To: Mark Brown , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Kevin Groeneveld Subject: [PATCH] spi: spi-imx: fix MX51_ECSPI_* macros when cs > 3 Date: Sat, 18 Mar 2023 18:21:32 -0400 Message-Id: <20230318222132.3373-1-kgroeneveld@lenbrook.com> X-Mailer: git-send-email 2.34.1 X-ClientProxiedBy: YT4PR01CA0050.CANPRD01.PROD.OUTLOOK.COM (2603:10b6:b01:111::10) To YT4PR01MB9670.CANPRD01.PROD.OUTLOOK.COM (2603:10b6:b01:e8::12) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: YT4PR01MB9670:EE_|YT2PR01MB8807:EE_ X-MS-Office365-Filtering-Correlation-Id: e75526e7-2994-4a57-44f4-08db27ff869a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: K36BTOPI+y0sdYRZ/FoSSBmMsDRizkiwAd1eXYIsWtFyoOQDIYLVBk9pVxiOKvYyZplsmSLi1XzTJmWNgsfrmNW8gZyhZzxszeLt9WQhA1LKlUnE4i2QwEkKKN14aRbcva+6fHkHDfHnUyE9PohguTuyBqkvNgbTL3swuTAtJkQFkaWUakub5Pat1aKpPyWhP3RSvFf8vh/PgkPRU/oJdS3pe9pmZtbY5Rlhwn8hVCb7tUIc2hpBocAjgfkr6L9o1fZnauGEBO2YQJ46746ygjq6gpN9NLqRF8UGg6Agm0mcQiNorZVC8Rao3fPaoO/O4iprLD9vQSEOisRAKqvCu/Vy6UUVh+NLuQ12IFOYN9OqLqFMNIb+YkK8NxcKRJIqkhLhhsqJ3kur6p7ufieugFXaTMIJA9qSZl+VJG1c+C8SU8HuuCEaNQuCuedpVdnEoDot00Cz94BYiuEUte7ick6+strw1yxpb9XuTs/+oPWk49GJ8hsg7jbunghHIJ5bcjvpRkVZIDokZhziiGPjdNkcthkEuQTezi+cMDzBxbMFT5qckeyGqsouzsnpDbnmpbXh97sd2spQm1FqrySMmvUT524pLQmAXK1ZoegKLYOerMl3j9gJ6Ei72Dk+ejQk3OZ8pvs61sfPD9BfL7lSpQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; 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The various MX51_ECSPI_* macros did not take this into consideration resulting in possible corruption of the configuration. For example for any cs value over 3 the SCLKPHA bits would not be set and other values in the register possibly corrupted. One way to fix this is to just mask the cs bits to 2 bits. This still allows all 4 native chip selects to work as well as gpio chip selects (which can use any of the 4 chip select configurations). Signed-off-by: Kevin Groeneveld --- drivers/spi/spi-imx.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index e4ccd0c329d0..c61c7ac4c70c 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c @@ -252,6 +252,18 @@ static bool spi_imx_can_dma(struct spi_controller *controller, struct spi_device return true; } +/* + * Note the number of natively supported chip selects for MX51 is 4. Some + * devices may have less actual SS pins but the register map supports 4. When + * using gpio chip selects the cs values passed into the macros below can go + * outside the range 0 - 3. We therefore need to limit the cs value to avoid + * corrupting bits outside the allocated locations. + * + * The simplest way to do this is to just mask the cs bits to 2 bits. This + * still allows all 4 native chip selects to work as well as gpio chip selects + * (which can use any of the 4 chip select configurations). + */ + #define MX51_ECSPI_CTRL 0x08 #define MX51_ECSPI_CTRL_ENABLE (1 << 0) #define MX51_ECSPI_CTRL_XCH (1 << 2) @@ -260,16 +272,16 @@ static bool spi_imx_can_dma(struct spi_controller *controller, struct spi_device #define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16) #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 -#define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) +#define MX51_ECSPI_CTRL_CS(cs) ((cs & 3) << 18) #define MX51_ECSPI_CTRL_BL_OFFSET 20 #define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20) #define MX51_ECSPI_CONFIG 0x0c -#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) -#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) -#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) -#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) -#define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20)) +#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs & 3) + 0)) +#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs & 3) + 4)) +#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs & 3) + 8)) +#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs & 3) + 12)) +#define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs & 3) + 20)) #define MX51_ECSPI_INT 0x10 #define MX51_ECSPI_INT_TEEN (1 << 0)