From patchwork Fri Jul 7 05:16:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveen Talari X-Patchwork-Id: 701468 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29A25C001B0 for ; Fri, 7 Jul 2023 05:17:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232052AbjGGFRZ (ORCPT ); Fri, 7 Jul 2023 01:17:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231912AbjGGFRU (ORCPT ); Fri, 7 Jul 2023 01:17:20 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 70637171D; Thu, 6 Jul 2023 22:17:19 -0700 (PDT) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3674K7s8021110; Fri, 7 Jul 2023 05:17:16 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=NCqK9AWW1jrILuN42ZzM3jJivYAr8GWtU2zu3BJnavc=; b=j3zWvdvezpuGymRJDQC04yX6fmK2vhsHcaOc0RMigr3OM2OvBl/I4TiFifcCSWD4HvCP p2hF6teivg0oqVswTBxxwzG+xlNA+m+ILt3KIoy7zBbanjcBVCs48LAs4/ndkE12/eW8 cLuqnSQdNj0bu5nDqdNxx1tG8p3nOdybKUsb/C3zcEupSuW5wv36VE5MEGYIkKcmFgdK eLbQ2QXsIspSGTX6UQw4ouyvaozYe0X59sSUfl6aGDUcnA2iIue7E4FjtF05AJnEwFwO LHq805zNR0pFv8RSAFUN2kBmgOktqvQ6iZPNsiWWQyr3UquUmpIh3wWV+tWgVNOPByFA ng== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rp96vrb1s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 07 Jul 2023 05:17:16 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3675HFr7010224 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 7 Jul 2023 05:17:15 GMT Received: from hu-ptalari-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Thu, 6 Jul 2023 22:17:11 -0700 From: Praveen Talari To: , , , , , , CC: , , , , Praveen Talari Subject: [PATCH v5 1/2] soc: qcom: geni-se: Add SPI Device mode support for GENI based QuPv3 Date: Fri, 7 Jul 2023 10:46:35 +0530 Message-ID: <20230707051636.5301-2-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230707051636.5301-1-quic_ptalari@quicinc.com> References: <20230707051636.5301-1-quic_ptalari@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: _y7Wucqs5Avz78vtqz3JbzkJj4PhYEEq X-Proofpoint-GUID: _y7Wucqs5Avz78vtqz3JbzkJj4PhYEEq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-07_02,2023-07-06_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 spamscore=0 mlxlogscore=999 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307070048 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Add device mode supported registers and masks. Signed-off-by: Praveen Talari --- v2 -> v3: - modified commit message to use device mode instead of slave mode v1 -> v2: - modified commit message --- include/linux/soc/qcom/geni-se.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni-se.h index 821a19135bb6..29e06905bc1f 100644 --- a/include/linux/soc/qcom/geni-se.h +++ b/include/linux/soc/qcom/geni-se.h @@ -35,6 +35,7 @@ enum geni_se_protocol_type { GENI_SE_UART, GENI_SE_I2C, GENI_SE_I3C, + GENI_SE_SPI_SLAVE, }; struct geni_wrapper; @@ -73,12 +74,14 @@ struct geni_se { /* Common SE registers */ #define GENI_FORCE_DEFAULT_REG 0x20 +#define GENI_OUTPUT_CTRL 0x24 #define SE_GENI_STATUS 0x40 #define GENI_SER_M_CLK_CFG 0x48 #define GENI_SER_S_CLK_CFG 0x4c #define GENI_IF_DISABLE_RO 0x64 #define GENI_FW_REVISION_RO 0x68 #define SE_GENI_CLK_SEL 0x7c +#define SE_GENI_CFG_SEQ_START 0x84 #define SE_GENI_DMA_MODE_EN 0x258 #define SE_GENI_M_CMD0 0x600 #define SE_GENI_M_CMD_CTRL_REG 0x604 @@ -111,6 +114,9 @@ struct geni_se { /* GENI_FORCE_DEFAULT_REG fields */ #define FORCE_DEFAULT BIT(0) +/* GENI_OUTPUT_CTRL fields */ +#define GENI_IO_MUX_0_EN BIT(0) + /* GENI_STATUS fields */ #define M_GENI_CMD_ACTIVE BIT(0) #define S_GENI_CMD_ACTIVE BIT(12) @@ -130,6 +136,9 @@ struct geni_se { /* GENI_CLK_SEL fields */ #define CLK_SEL_MSK GENMASK(2, 0) +/* SE_GENI_CFG_SEQ_START fields */ +#define START_TRIGGER BIT(0) + /* SE_GENI_DMA_MODE_EN */ #define GENI_DMA_MODE_EN BIT(0)