From patchwork Tue Jan 30 09:40:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfram Sang X-Patchwork-Id: 769460 Received: from mail.zeus03.de (www.zeus03.de [194.117.254.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBEFE60BB0 for ; Tue, 30 Jan 2024 09:41:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=194.117.254.33 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706607668; cv=none; b=S9E/jkFvc+0WzPnpUfViYQEzSp4DFLi4t5QXpXmJlCbrQC8VVnFP6f2LlOQbXISFtcnltNRQ8OUtFo34U6kBV3Wtp7qblpUZlxLo6w/S6+f0O5JXpn7/M9rl4kIfBQT4GFRMuizd7WbhHrJcwvJ8PkPI/vgMmghGJRNj19j37dg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706607668; c=relaxed/simple; bh=2OHLsZS4PsJMPwjOKM6F0kv6fbGghDQNdDA7mW+z63U=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=YwYyEKiqLAK1maDDdbumruQT00ziCUm84F9ETsRM+0KZRiCVj3ndrndvqFVp9msnDvhV+XRUsI/DvgcY0jtGflCCwLgj3YfI1ZWljRbtMPuFbo2ZnSBEB2n4PRrR0fjaJsDikNUoxxUVDet3goqP5wq5bjaEwqaRiyrCixkXS58= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sang-engineering.com; spf=pass smtp.mailfrom=sang-engineering.com; dkim=pass (2048-bit key) header.d=sang-engineering.com header.i=@sang-engineering.com header.b=PM033RNt; arc=none smtp.client-ip=194.117.254.33 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sang-engineering.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sang-engineering.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sang-engineering.com header.i=@sang-engineering.com header.b="PM033RNt" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= sang-engineering.com; h=from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; s=k1; bh=AzSdhb1EFgr8m9 GCPzSJauJkFDRxOixnrXfrfcPby5k=; b=PM033RNtlmu+MGufEY5zm5sFAYMUyh jGBh4rzolkWqBQre7/9t4OI+XsEPVYVlGZBfnT8+O1jtgJm36T0MnQRKDVxpoQf+ lr9ufsjd1RSLGQx9x4OaRGVZBnxDI1iJWvXr+LeKEcIPH5/u48jPDKYcyzPvhfg6 JzSCHoV7eJVbfuJRKEPPtOESzWyeBpQf/upvVLNUjfS4hMFjVOqaPmhMZLqlap4h GeIOZMfODM2UjMpwdnj386or9JvL5vSmYBOUqk36mH2pMIFD82MmIrd+3XBrFvUy 12l1Du0TU7fVPUgUKwdkuZq6zFXj0TmSOCVC3LaIhi5a6wGqlzzJvqlg== Received: (qmail 2783205 invoked from network); 30 Jan 2024 10:41:00 +0100 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 30 Jan 2024 10:41:00 +0100 X-UD-Smtp-Session: l3s3148p1@lKVcjyYQVJlehhtJ From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: Wolfram Sang , Mark Brown , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] spi: sh-msiof: avoid integer overflow in constants Date: Tue, 30 Jan 2024 10:40:53 +0100 Message-Id: <20240130094053.10672-1-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.39.2 Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 cppcheck rightfully warned: drivers/spi/spi-sh-msiof.c:792:28: warning: Signed integer overflow for expression '7<<29'. [integerOverflow] sh_msiof_write(p, SIFCTR, SIFCTR_TFWM_1 | SIFCTR_RFWM_1); Signed-off-by: Wolfram Sang --- drivers/spi/spi-sh-msiof.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index cfc3b1ddbd22..6f12e4fb2e2e 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -136,14 +136,14 @@ struct sh_msiof_spi_priv { /* SIFCTR */ #define SIFCTR_TFWM_MASK GENMASK(31, 29) /* Transmit FIFO Watermark */ -#define SIFCTR_TFWM_64 (0 << 29) /* Transfer Request when 64 empty stages */ -#define SIFCTR_TFWM_32 (1 << 29) /* Transfer Request when 32 empty stages */ -#define SIFCTR_TFWM_24 (2 << 29) /* Transfer Request when 24 empty stages */ -#define SIFCTR_TFWM_16 (3 << 29) /* Transfer Request when 16 empty stages */ -#define SIFCTR_TFWM_12 (4 << 29) /* Transfer Request when 12 empty stages */ -#define SIFCTR_TFWM_8 (5 << 29) /* Transfer Request when 8 empty stages */ -#define SIFCTR_TFWM_4 (6 << 29) /* Transfer Request when 4 empty stages */ -#define SIFCTR_TFWM_1 (7 << 29) /* Transfer Request when 1 empty stage */ +#define SIFCTR_TFWM_64 (0UL << 29) /* Transfer Request when 64 empty stages */ +#define SIFCTR_TFWM_32 (1UL << 29) /* Transfer Request when 32 empty stages */ +#define SIFCTR_TFWM_24 (2UL << 29) /* Transfer Request when 24 empty stages */ +#define SIFCTR_TFWM_16 (3UL << 29) /* Transfer Request when 16 empty stages */ +#define SIFCTR_TFWM_12 (4UL << 29) /* Transfer Request when 12 empty stages */ +#define SIFCTR_TFWM_8 (5UL << 29) /* Transfer Request when 8 empty stages */ +#define SIFCTR_TFWM_4 (6UL << 29) /* Transfer Request when 4 empty stages */ +#define SIFCTR_TFWM_1 (7UL << 29) /* Transfer Request when 1 empty stage */ #define SIFCTR_TFUA_MASK GENMASK(26, 20) /* Transmit FIFO Usable Area */ #define SIFCTR_TFUA_SHIFT 20 #define SIFCTR_TFUA(i) ((i) << SIFCTR_TFUA_SHIFT)