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[211.75.127.162]) by smtp.gmail.com with ESMTPSA id 31-20020a630d5f000000b005c21c23180bsm11972741pgn.76.2024.02.01.01.44.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 01:44:01 -0800 (PST) Received: from hqs-appsw-appswa2.mp600.macronix.com (linux-patcher [172.17.236.35]) by twhmp6px (Postfix) with ESMTPS id 527878095A; Thu, 1 Feb 2024 17:50:02 +0800 (CST) From: Jaime Liao To: linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org, tudor.ambarus@linaro.org, pratyush@kernel.org, mwalle@kernel.org, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, broonie@kernel.org Cc: leoyu@mxic.com.tw, jaimeliao@mxic.com.tw Subject: [PATCH v8 3/9] mtd: spi-nor: core: Allow specifying the byte order in Octal DTR mode Date: Thu, 1 Feb 2024 17:43:47 +0800 Message-Id: <20240201094353.33281-4-jaimeliao.tw@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240201094353.33281-1-jaimeliao.tw@gmail.com> References: <20240201094353.33281-1-jaimeliao.tw@gmail.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: JaimeLiao Macronix swaps bytes on a 16-bit boundary when configured in Octal DTR. The byte order of 16-bit words is swapped when read or written in 8D-8D-8D mode compared to STR modes. Allow operations to specify the byte order in DTR mode, so that controllers can swap the bytes back at run-time to address the flash's endianness requirements, if they are capable. If the controllers are not capable of swapping the bytes, the protocol is downgrade via spi_nor_spimem_adjust_hwcaps(). When available, the swapping of the bytes is always done regardless if it's a data or register access, so that we comply with the JESD216 requirements: "Byte order of 16-bit words is swapped when read in 8D-8D-8D mode compared to 1-1-1". Merge Tudor's patch and add modifications for suiting newer version of Linux kernel. Suggested-by: Michael Walle Signed-off-by: Tudor Ambarus Signed-off-by: JaimeLiao --- drivers/mtd/spi-nor/core.c | 5 +++++ drivers/mtd/spi-nor/core.h | 1 + 2 files changed, 6 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 4129764fad8c..0076007e1cde 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -113,6 +113,11 @@ void spi_nor_spimem_setup_op(const struct spi_nor *nor, op->cmd.opcode = (op->cmd.opcode << 8) | ext; op->cmd.nbytes = 2; } + + /* SWAP16 is only applicable when Octal DTR mode */ + if (nor->read_proto == SNOR_PROTO_8_8_8_DTR) + if (nor->flags & SNOR_F_SWAP16) + op->data.swap16 = true; } /** diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index d36c0e072954..3c5190ac0a79 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -140,6 +140,7 @@ enum spi_nor_option_flags { SNOR_F_RWW = BIT(14), SNOR_F_ECC = BIT(15), SNOR_F_NO_WP = BIT(16), + SNOR_F_SWAP16 = BIT(17), }; struct spi_nor_read_command {