From patchwork Fri Apr 5 15:02:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 786707 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8565316F915; Fri, 5 Apr 2024 15:02:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712329344; cv=none; b=CJ0cu/7Qn8U7kiBXq+eZjVKrPT9c40MHnhyJUD+VgpL1ravCevYhod+J659Irp/Y0waPNfol4syVBPO+jLNt7jake43JG2kSaOjUXfg4TV18aJoE9Zjnr59ogI7+cDEod/29oE2HEWD5H/C7v0o1eGhlDMI4cg7AEY3ZG2TXNr4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712329344; c=relaxed/simple; bh=Ar8fBamV+L9arbDgrVzcqRsw0ePZyBU1WIsWO6nxU6U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XUMy5Ia6IyYpBsrGZolEcbxm2LohCXv+GK+HXpkIj7dEzmXWx7npQKGg8ZZDUJFDQ/Umb3Gw/NbH6YOwRuGtXzidhDp6RcivFFevsj42cjS3xTyQMf1mp9i5mWp7nhxwv9cFFHvlZPQ2EkAjELvDHIhTFW5eCGhK/VMTp0VBzyE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=NynxWG/G; arc=none smtp.client-ip=217.70.183.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="NynxWG/G" Received: by mail.gandi.net (Postfix) with ESMTPSA id 63B991BF209; Fri, 5 Apr 2024 15:02:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1712329339; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Bw7wAnZBCykLnl0Z3hjw2J86RWa0b9ykf06ta9MdRww=; b=NynxWG/G+Vi1I1vRSv3V+VS+uycDUWI3UMhT1mgbqi2cnPbwAAm6cPKJ7OSlMI5M4JGFnW BOwY/vrzJ489BFeb4O1VgyxyrA0NjazrGoA5wICWvb6/BTt4UynaTwo18hd5uS2tGxZLZt ThoQoGBCbiPQz+RMZ0mUQ3yPcTA5cxWQUY7i6YRqlMU5jnFbdplNoBG7lQFDDa5PDN1SYM xxH1yT9OZOpyZAK1qqfzXgXJbm59UEFyLV2S7zRGatrCsC1lugDDFgbbzJUj621aq5ModA LesEkhdCte5jprORy1eAGECcO8ejvoVV/bCqdXCkXQfCH5UV1IcQ6HiEkiBTzQ== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Fri, 05 Apr 2024 17:02:17 +0200 Subject: [PATCH v2 07/11] spi: cadence-qspi: add no-IRQ mode to indirect reads Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240405-cdns-qspi-mbly-v2-7-956679866d6d@bootlin.com> References: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com> In-Reply-To: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vaishnav Achath , Thomas Bogendoerfer , Rob Herring Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Vladimir Kondratiev , Gregory CLEMENT , Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.13.0 X-GND-Sasl: theo.lebrun@bootlin.com Support reads through polling, without any IRQ. The main reason is performance; profiling shows that the first IRQ comes quickly on our specific hardware. Once this IRQ arrives, we poll until all data is retrieved. Avoid initial sleep to reduce IRQ count. Hide this behavior behind a quirk flag. This is confirmed through micro-benchmarks, but also end-to-end performance tests. Mobileye EyeQ5, octal flash, reading 235M on a UBIFS filesystem: - No optimizations, ~10.34s, ~22.7 MB/s, 199230 IRQs - CQSPI_SLOW_SRAM, ~10.34s, ~22.7 MB/s, 70284 IRQs - CQSPI_RD_NO_IRQ, ~9.37s, ~25.1 MB/s, 521 IRQs Signed-off-by: Théo Lebrun --- drivers/spi/spi-cadence-quadspi.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 55d20d565fe5..ebb8c35f50fd 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -43,6 +43,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <= SPI_CS_CNT_MAX); #define CQSPI_SLOW_SRAM BIT(4) #define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) #define CQSPI_DETECT_FIFO_DEPTH BIT(6) +#define CQSPI_RD_NO_IRQ BIT(7) /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -703,6 +704,7 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, const size_t n_rx) { struct cqspi_st *cqspi = f_pdata->cqspi; + bool use_irq = !(cqspi->ddata && cqspi->ddata->quirks & CQSPI_RD_NO_IRQ); struct device *dev = &cqspi->pdev->dev; void __iomem *reg_base = cqspi->iobase; void __iomem *ahb_base = cqspi->ahb_base; @@ -726,17 +728,20 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, * all the read interrupts disabled for max performance. */ - if (!cqspi->slow_sram) + if (use_irq && cqspi->slow_sram) + writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK); + else if (use_irq) writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK); else - writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK); + writel(0, reg_base + CQSPI_REG_IRQMASK); reinit_completion(&cqspi->transfer_complete); writel(CQSPI_REG_INDIRECTRD_START_MASK, reg_base + CQSPI_REG_INDIRECTRD); while (remaining > 0) { - if (!wait_for_completion_timeout(&cqspi->transfer_complete, + if (use_irq && + !wait_for_completion_timeout(&cqspi->transfer_complete, msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) ret = -ETIMEDOUT; @@ -778,7 +783,7 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, bytes_to_read = cqspi_get_rd_sram_level(cqspi); } - if (remaining > 0) { + if (use_irq && remaining > 0) { reinit_completion(&cqspi->transfer_complete); if (cqspi->slow_sram) writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK);