From patchwork Thu May 9 01:05:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Witold Sadowski X-Patchwork-Id: 796863 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76B4613A879; Thu, 9 May 2024 01:05:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715216761; cv=none; b=FxU7gzbxXCEYllFz/s7EDRyWXNadngYN2Pho4VMTXXAyqRtpgkw/VxfHnyrw4X2QYJ/vHfgVoqch/VzP4LdeXG0uUvDJzEG+lRSXhu6q4p2IJvIkEs7ERaWTRzmr8cgQSHzLkIW9y8AeKojlgmfyFu6/JCseqA4ta7p/Wht9XME= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715216761; c=relaxed/simple; bh=TLv2bcYdLVp9hvvristhTJBcAcbK6tgUlV4iS6iOHBQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=eEuoZjvT65fQtij+wsvT2hM571si+Lca7D1xcHLjWeyO/3WKMpQ+lr4BLRV4rcuMq3mUg7YRoZCmSLjHWHaQv/U3TtLCNXz0TOTm7QCq2xEgKqeSKQhh8G97XnUxS2L69vvj/i/lIxrDodsNZbktuIGiXSG8OT9TaFAjONCvHaU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=jMuVB9K9; arc=none smtp.client-ip=67.231.148.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="jMuVB9K9" Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 448NXnkX002999; Wed, 8 May 2024 18:05:55 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=79Z78MajtPZ9LSvhPdND6xhDzCkLBwECFqv7gjrVclY=; b=jMu VB9K9G0TIhnvoNkNSNvRzfXHlI7qFzhDAtSDpPbrz1cTbJdm1qb8lHG6cNKH+E8J oN5ZWoeMnv2UhBbWwEAjjwUSkEKP85viKJMYf1BqbtjEBln9AybEuLUiR9PTmvtN uIoj9YSJvERGlHCfJS8O1pKKqQ5wr61qRDGUcnY0PBIo5e4NKXXZlK5OpAENibbM Rfcql1zDJ6TJmSZZaoEo+YDThDsM2b8hfDYCdysa7bivnAMK7oMXwFzSekVRpkCf xLYXKqWLYZceS4AWya6AN/BWMPoCHVe5uOFNgO+uDBcr/35lGVW77oU9M01DF+in 8HiH4gWDsPFhDhFZHjg== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3y0b2d2g1f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 08 May 2024 18:05:55 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 8 May 2024 18:05:54 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 8 May 2024 18:05:54 -0700 Received: from Dell2s-9.sclab.marvell.com (unknown [10.110.150.250]) by maili.marvell.com (Postfix) with ESMTP id 502365B694D; Wed, 8 May 2024 18:05:54 -0700 (PDT) From: Witold Sadowski To: , , CC: , , , , , Piyush Malgujar , "Witold Sadowski" Subject: [PATCH v4 4/5] spi: cadence: Allow to read basic xSPI configuration from ACPI Date: Wed, 8 May 2024 18:05:22 -0700 Message-ID: <20240509010523.3152264-5-wsadowski@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240509010523.3152264-1-wsadowski@marvell.com> References: <20240509010523.3152264-1-wsadowski@marvell.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: xP2ux3N7bYNQ1f98Tta26bUKa0Uh1k6a X-Proofpoint-ORIG-GUID: xP2ux3N7bYNQ1f98Tta26bUKa0Uh1k6a X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-08_10,2024-05-08_01,2023-05-22_02 From: Piyush Malgujar These changes enables to read the configs from ACPI tables as required for successful probing in ACPI uefi environment. In case of ACPI disabled/dts based environment, it will continue to read configs from dts as before Signed-off-by: Piyush Malgujar Signed-off-by: Witold Sadowski --- drivers/spi/spi-cadence-xspi.c | 84 +++++++++++++++++++++++++++++++--- 1 file changed, 77 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-cadence-xspi.c b/drivers/spi/spi-cadence-xspi.c index 4bfcfa2f8835..f6bae59b34e5 100644 --- a/drivers/spi/spi-cadence-xspi.c +++ b/drivers/spi/spi-cadence-xspi.c @@ -2,6 +2,7 @@ // Cadence XSPI flash controller driver // Copyright (C) 2020-21 Cadence +#include #include #include #include @@ -14,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -647,6 +649,67 @@ static int cdns_xspi_mem_op(struct cdns_xspi_dev *cdns_xspi, (dir != SPI_MEM_NO_DATA)); } +#ifdef CONFIG_ACPI +static bool cdns_xspi_supports_op(struct spi_mem *mem, + const struct spi_mem_op *op) +{ + struct spi_device *spi = mem->spi; + const union acpi_object *obj; + struct acpi_device *adev; + + adev = ACPI_COMPANION(&spi->dev); + + if (!acpi_dev_get_property(adev, "spi-tx-bus-width", ACPI_TYPE_INTEGER, + &obj)) { + switch (obj->integer.value) { + case 1: + break; + case 2: + spi->mode |= SPI_TX_DUAL; + break; + case 4: + spi->mode |= SPI_TX_QUAD; + break; + case 8: + spi->mode |= SPI_TX_OCTAL; + break; + default: + dev_warn(&spi->dev, + "spi-tx-bus-width %lld not supported\n", + obj->integer.value); + break; + } + } + + if (!acpi_dev_get_property(adev, "spi-rx-bus-width", ACPI_TYPE_INTEGER, + &obj)) { + switch (obj->integer.value) { + case 1: + break; + case 2: + spi->mode |= SPI_RX_DUAL; + break; + case 4: + spi->mode |= SPI_RX_QUAD; + break; + case 8: + spi->mode |= SPI_RX_OCTAL; + break; + default: + dev_warn(&spi->dev, + "spi-rx-bus-width %lld not supported\n", + obj->integer.value); + break; + } + } + + if (!spi_mem_default_supports_op(mem, op)) + return false; + + return true; +} +#endif + static int cdns_xspi_mem_op_execute(struct spi_mem *mem, const struct spi_mem_op *op) { @@ -670,6 +733,9 @@ static int cdns_xspi_adjust_mem_op_size(struct spi_mem *mem, struct spi_mem_op * } static const struct spi_controller_mem_ops cadence_xspi_mem_ops = { +#ifdef CONFIG_ACPI + .supports_op = cdns_xspi_supports_op, +#endif .exec_op = cdns_xspi_mem_op_execute, .adjust_op_size = cdns_xspi_adjust_mem_op_size, }; @@ -721,21 +787,20 @@ static irqreturn_t cdns_xspi_irq_handler(int this_irq, void *dev) static int cdns_xspi_of_get_plat_data(struct platform_device *pdev) { - struct device_node *node_prop = pdev->dev.of_node; - struct device_node *node_child; + struct fwnode_handle *fwnode_child; unsigned int cs; - for_each_child_of_node(node_prop, node_child) { - if (!of_device_is_available(node_child)) + device_for_each_child_node(&pdev->dev, fwnode_child) { + if (!fwnode_device_is_available(fwnode_child)) continue; - if (of_property_read_u32(node_child, "reg", &cs)) { + if (fwnode_property_read_u32(fwnode_child, "reg", &cs)) { dev_err(&pdev->dev, "Couldn't get memory chip select\n"); - of_node_put(node_child); + fwnode_handle_put(fwnode_child); return -ENXIO; } else if (cs >= CDNS_XSPI_MAX_BANKS) { dev_err(&pdev->dev, "reg (cs) parameter value too large\n"); - of_node_put(node_child); + fwnode_handle_put(fwnode_child); return -ENXIO; } } @@ -789,6 +854,11 @@ static int cdns_xspi_probe(struct platform_device *pdev) SPI_MODE_0 | SPI_MODE_3; drv_data = of_device_get_match_data(dev); + if (!drv_data) { + drv_data = acpi_device_get_match_data(dev); + if (!drv_data) + return -ENODEV; + } host->mem_ops = &cadence_xspi_mem_ops; host->dev.of_node = pdev->dev.of_node;