From patchwork Fri Nov 15 20:18:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Lechner X-Patchwork-Id: 843778 Received: from mail-oo1-f45.google.com (mail-oo1-f45.google.com [209.85.161.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99FFF1E5733 for ; Fri, 15 Nov 2024 20:18:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.161.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731701941; cv=none; b=Qo8zzeg5EQg2+bi3QFjHlIu24Mh7e+7C+DcEvwdeQIMEpiOQknl6CcrJoYZfIY1Otr+WJgvoqsCTEUvlmhvOxF7qqn10G1u4/01gJqw4cwgCAUX7h1nwVz0zs+30EG/9sk3uVBw3Kb8rc66oVqN7+oxrCLkctwysRZ4aSVnxCYo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731701941; c=relaxed/simple; bh=EOrNOpVWi5EnXRP0UHniNwzvlTT9ETmHZWZMFC0dRL4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oaFajRRWlsjd1lTPJ7HPTfUH9lTqN30fqS1ok6MzVXwGMxEEa+lU2rAcsBC0y6cijyOB8ClnOoFtQ2FZ9bsl/S6zzkKmN9W5vHolx8zYzKEHSlwFntqSIQAeXoiZMnFpbtlGf7IMY9oer7RUmD3jAY2yGIY5bC5I0htr9/CkuNI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=k1rg/IUX; arc=none smtp.client-ip=209.85.161.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="k1rg/IUX" Received: by mail-oo1-f45.google.com with SMTP id 006d021491bc7-5ee645cf763so1181051eaf.2 for ; Fri, 15 Nov 2024 12:18:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1731701938; x=1732306738; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=t7IS98DAXMrAPkmBeqmORVUNuKNfq4F6AMKjYOvJmjo=; b=k1rg/IUXPQIFLvPDLcEDyAKj8U007qJy/DfuA26fiGdk5FD0ZVt8Po4OtNm8udWu7E II1dY03Zu548P0r62f8RGgt8nzKZCA/ehTpcBRr1k6Ae66YUCv3PLRTV89Fuk6cdGNBN r9IDf7v5rOkh4Y95oPRdx8PfnGpMtZG/sCvNTAcLCUJxLxHxLltAu/5Az8Gq8QwxnXg0 MbHsc+O8Il3A0K2lZ99iSZnG9dSKv51Jxt+S61fM7CgjocGp94G3xU3VxUr1RJLyYm3I x8HXN1BJ5AMZYijdfB2xJxNtgxUvZAOXpSIukuUmqpAZZw7AeZX9Md1wx/zL0hKcqlhH FgoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731701938; x=1732306738; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=t7IS98DAXMrAPkmBeqmORVUNuKNfq4F6AMKjYOvJmjo=; b=c4DoxvVkrN/LfED8zN3s/6OOYVNaedqcogDu1n5yvnmvLnJj86+HFwcY+06H8e/6jC ooou6ZtN6ir50iWTUTuxigz425jS4ySRqbNOPOYWLGXSF2Da+PJ80p8Sht0EjJYNe76N yV1koLg2QksgA82wFeusJNenchG6Ea5DATLnMwwU2L+tlfLhUsJpZtJlAGgDjmAzY8h1 YZ+s/kJpSbs0cKiJ7yKYAgjOR/EbQ9IRzi82UhAhFTSTDE3vMpK0YKBVeUgg4RY7gE1F VeKUr4m7hZmho8m+EX6knavKtvGeDNEG2yFCYThp1ONzVkDXgMx3sRXP7QxoIbnIPJwc Kq8g== X-Forwarded-Encrypted: i=1; AJvYcCVjSZ8/0+y+ioxKg8udQA4mBj15GENvbXU0lDvaQwAcJCXNnnPK3ecC8RCmwiSZQjIogWJPnsmdps4=@vger.kernel.org X-Gm-Message-State: AOJu0YyP1h8bXy0lHVHvC3T9joyCbr7qs1kl9/RMu+QIwCHOngEdjavw ShWS1HpIsVzR2KDfEcdw23vzJZdHWgSTQI/B0hZBuli3vhiDkzRzgerkd8gThRI= X-Google-Smtp-Source: AGHT+IFHeOlL2szpnhn4w4uUrf+kcWOlOBXXrP/zlahKkvyGqcUo6Oac5nm5vBqKn+mlHYLrAPqrcQ== X-Received: by 2002:a05:6820:4c88:b0:5eb:c6ba:783b with SMTP id 006d021491bc7-5eeab29d4a5mr3913047eaf.1.1731701937692; Fri, 15 Nov 2024 12:18:57 -0800 (PST) Received: from [127.0.1.1] (ip98-183-112-25.ok.ok.cox.net. [98.183.112.25]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-71a780ea62esm748978a34.5.2024.11.15.12.18.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Nov 2024 12:18:57 -0800 (PST) From: David Lechner Date: Fri, 15 Nov 2024 14:18:44 -0600 Subject: [PATCH v5 05/16] spi: offload-trigger: add PWM trigger driver Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241115-dlech-mainline-spi-engine-offload-2-v5-5-bea815bd5ea5@baylibre.com> References: <20241115-dlech-mainline-spi-engine-offload-2-v5-0-bea815bd5ea5@baylibre.com> In-Reply-To: <20241115-dlech-mainline-spi-engine-offload-2-v5-0-bea815bd5ea5@baylibre.com> To: Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Nuno_S=C3=A1?= Cc: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Michael Hennerich , Lars-Peter Clausen , David Jander , Martin Sperl , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-pwm@vger.kernel.org, David Lechner X-Mailer: b4 0.14.1 Add a new driver for a generic PWM trigger for SPI offloads. Signed-off-by: David Lechner Reviewed-by: Jonathan Cameron --- v5 changes: * Updated to accommodate changes in other patches in this series. * Add MAINTAINERS entry. v4 changes: new patch in v4 --- MAINTAINERS | 1 + drivers/spi/Kconfig | 12 +++ drivers/spi/Makefile | 3 + drivers/spi/spi-offload-trigger-pwm.c | 162 ++++++++++++++++++++++++++++++++++ 4 files changed, 178 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a43532a1edde..36a40aaa026a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22023,6 +22023,7 @@ SPI OFFLOAD R: David Lechner F: Documentation/devicetree/bindings/spi/trigger-pwm.yaml F: Documentation/devicetree/bindings/spi/trigger-source.yaml +F: drivers/spi/spi-offload-trigger-pwm.c F: drivers/spi/spi-offload.c F: include/linux/spi/spi-offload.h K: spi_offload diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index cdc483b0ec5c..867d4b55bef9 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -1308,4 +1308,16 @@ endif # SPI_SLAVE config SPI_DYNAMIC def_bool ACPI || OF_DYNAMIC || SPI_SLAVE +if SPI_OFFLOAD + +comment "SPI Offload triggers" + +config SPI_OFFLOAD_TRIGGER_PWM + tristate "SPI offload trigger using PWM" + depends on PWM + help + Generic SPI offload trigger implemented using PWM output. + +endif # SPI_OFFLOAD + endif # SPI diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 39025ae5364d..9396d32e1994 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -163,3 +163,6 @@ obj-$(CONFIG_SPI_AMD) += spi-amd.o # SPI slave protocol handlers obj-$(CONFIG_SPI_SLAVE_TIME) += spi-slave-time.o obj-$(CONFIG_SPI_SLAVE_SYSTEM_CONTROL) += spi-slave-system-control.o + +# SPI offload triggers +obj-$(CONFIG_SPI_OFFLOAD_TRIGGER_PWM) += spi-offload-trigger-pwm.o diff --git a/drivers/spi/spi-offload-trigger-pwm.c b/drivers/spi/spi-offload-trigger-pwm.c new file mode 100644 index 000000000000..7e1b4a80becc --- /dev/null +++ b/drivers/spi/spi-offload-trigger-pwm.c @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024 Analog Devices Inc. + * Copyright (C) 2024 BayLibre, SAS + * + * Generic PWM trigger for SPI offload. + */ + +#include +#include +#include +#include +#include + +struct spi_offload_trigger_pwm_state { + struct device *dev; + struct pwm_device *pwm; +}; + +static bool spi_offload_trigger_pwm_match(struct spi_offload_trigger *trigger, + enum spi_offload_trigger_type type, + u64 *args, u32 nargs) +{ + if (nargs) + return false; + + return type == SPI_OFFLOAD_TRIGGER_PERIODIC; +} + +static int spi_offload_trigger_pwm_validate(struct spi_offload_trigger *trigger, + struct spi_offload_trigger_config *config) +{ + struct spi_offload_trigger_pwm_state *st = spi_offload_trigger_get_priv(trigger); + struct spi_offload_trigger_periodic *periodic = &config->periodic; + struct pwm_waveform wf = { }; + int ret; + + if (config->type != SPI_OFFLOAD_TRIGGER_PERIODIC) + return -EINVAL; + + if (!periodic->frequency_hz) + return -EINVAL; + + wf.period_length_ns = DIV_ROUND_UP_ULL(NSEC_PER_SEC, periodic->frequency_hz); + /* REVISIT: 50% duty-cycle for now - may add config parameter later */ + wf.duty_length_ns = wf.period_length_ns / 2; + + ret = pwm_round_waveform_might_sleep(st->pwm, &wf); + if (ret < 0) + return ret; + + periodic->frequency_hz = DIV_ROUND_UP_ULL(NSEC_PER_SEC, wf.period_length_ns); + + return 0; +} + +static int spi_offload_trigger_pwm_enable(struct spi_offload_trigger *trigger, + struct spi_offload_trigger_config *config) +{ + struct spi_offload_trigger_pwm_state *st = spi_offload_trigger_get_priv(trigger); + struct spi_offload_trigger_periodic *periodic = &config->periodic; + struct pwm_waveform wf = { }; + + if (config->type != SPI_OFFLOAD_TRIGGER_PERIODIC) + return -EINVAL; + + if (!periodic->frequency_hz) + return -EINVAL; + + wf.period_length_ns = DIV_ROUND_UP_ULL(NSEC_PER_SEC, periodic->frequency_hz); + /* REVISIT: 50% duty-cycle for now - may add config parameter later */ + wf.duty_length_ns = wf.period_length_ns / 2; + + return pwm_set_waveform_might_sleep(st->pwm, &wf, false); +} + +static void spi_offload_trigger_pwm_disable(struct spi_offload_trigger *trigger) +{ + struct spi_offload_trigger_pwm_state *st = spi_offload_trigger_get_priv(trigger); + struct pwm_waveform wf; + int ret; + + ret = pwm_get_waveform_might_sleep(st->pwm, &wf); + if (ret < 0) { + dev_err(st->dev, "failed to get waveform: %d\n", ret); + return; + } + + wf.duty_length_ns = 0; + + ret = pwm_set_waveform_might_sleep(st->pwm, &wf, false); + if (ret < 0) + dev_err(st->dev, "failed to disable PWM: %d\n", ret); +} + +static const struct spi_offload_trigger_ops spi_offload_trigger_pwm_ops = { + .match = spi_offload_trigger_pwm_match, + .validate = spi_offload_trigger_pwm_validate, + .enable = spi_offload_trigger_pwm_enable, + .disable = spi_offload_trigger_pwm_disable, +}; + +static void spi_offload_trigger_pwm_release(void *data) +{ + pwm_disable(data); +} + +static int spi_offload_trigger_pwm_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct spi_offload_trigger_info info = { + .fwnode = dev_fwnode(dev), + .ops = &spi_offload_trigger_pwm_ops, + }; + struct spi_offload_trigger_pwm_state *st; + struct pwm_state state; + int ret; + + st = devm_kzalloc(&pdev->dev, sizeof(*st), GFP_KERNEL); + if (!st) + return -ENOMEM; + + info.priv = st; + st->dev = dev; + + st->pwm = devm_pwm_get(&pdev->dev, NULL); + if (IS_ERR(st->pwm)) + return dev_err_probe(dev, PTR_ERR(st->pwm), "failed to get PWM\n"); + + /* init with duty_cycle = 0, output enabled to ensure trigger off */ + pwm_init_state(st->pwm, &state); + state.enabled = true; + + ret = pwm_apply_might_sleep(st->pwm, &state); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to apply PWM state\n"); + + ret = devm_add_action_or_reset(dev, spi_offload_trigger_pwm_release, st->pwm); + if (ret) + return ret; + + return devm_spi_offload_trigger_register(dev, &info); +} + +static const struct of_device_id spi_offload_trigger_pwm_of_match_table[] = { + { .compatible = "trigger-pwm" }, + { } +}; +MODULE_DEVICE_TABLE(of, spi_offload_trigger_pwm_of_match_table); + +static struct platform_driver spi_offload_trigger_pwm_driver = { + .driver = { + .name = "trigger-pwm", + .of_match_table = spi_offload_trigger_pwm_of_match_table, + }, + .probe = spi_offload_trigger_pwm_probe, +}; +module_platform_driver(spi_offload_trigger_pwm_driver); + +MODULE_AUTHOR("David Lechner "); +MODULE_DESCRIPTION("Generic PWM trigger"); +MODULE_LICENSE("GPL");