From patchwork Tue Jan 28 08:17:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 860599 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8FEE1DED6C; Tue, 28 Jan 2025 08:22:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738052531; cv=none; b=HdbrTCz9a54LtLZpUDRpFkxCLa/L95zEJBClngQN6mTDnux3TDTmpeZQ+gsdXqYvX8JnnBnu87BvJyb4YJnaRdPIgoQkxEnryOawJKilWqqUEYa4MUcpUw7FWRmIWXLQgDZW0O8ofdDKnlx/d1ouRDhQj5NCQNZNGVTdaW04MVc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738052531; c=relaxed/simple; bh=m6I3mC8dyqaEcC9Fxrzwn4B91/qA68y80VdD6bfX5X4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=oaVVh/z7pva2v62TftF1DEVx6n6pIlLEJAJGcwdpAJ8N4w9WlMHINuvB+TkM1Oh4lLrsknXl3JGW3sFYHe7TicSMk/PMIPDVPtIcxbkWL+VvnO+7cMzRU+aFT3gy6Cru0IUPnmbqGkHUgO1igve1ne9eWntORfIACGBNJerP0GA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=bBOzCgX+; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="bBOzCgX+" Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 50S21B39013991; Tue, 28 Jan 2025 09:21:28 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= feDQEg72QVpJ9CVOEroQqgaGzK4obTSQ+cagaGstWic=; b=bBOzCgX+59XUOJkr 4PiUgzbvENEkx5kTCigQs5XE/i74/RoqikYnqDaa0clSxWgSo8V+AjFYnZfZEK+F oFAyx0J/AU8dz+8SS4XlAw7jTzIc2JEOrSfuZTg8CvnTTmKGs6o9JkaLQ1b06of7 rkj/zjeuBMjNouLBRZdj/k9iEd3ELeFyVtU033ZtjHmJRrEE1SFaNb1AAKpR7fpf FeO4lLG0xnFBwS7gLEaAeqIhPNQDW2J4T2l40U60awiFgSb0bHun5fm58A0FtbSu TrRr3lFCI7BRwyH1Rr5J5Z+H1lad0/ILC12GWj1OppGb6LCk2p7rI2PHERsY6Z8a 4NWfqQ== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 44embfs6pq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 28 Jan 2025 09:21:28 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 2227240053; Tue, 28 Jan 2025 09:20:05 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 3F10129C5E2; Tue, 28 Jan 2025 09:17:43 +0100 (CET) Received: from localhost (10.48.87.62) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Tue, 28 Jan 2025 09:17:42 +0100 From: To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Torgue , Philipp Zabel , Maxime Coquelin , Greg Kroah-Hartman , Arnd Bergmann , Catalin Marinas , Will Deacon CC: , , , , , , Subject: [PATCH v2 1/9] dt-bindings: spi: Add STM32 OSPI controller Date: Tue, 28 Jan 2025 09:17:23 +0100 Message-ID: <20250128081731.2284457-2-patrice.chotard@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250128081731.2284457-1-patrice.chotard@foss.st.com> References: <20250128081731.2284457-1-patrice.chotard@foss.st.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SAFCAS1NODE1.st.com (10.75.90.11) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-28_02,2025-01-27_01,2024-11-22_01 From: Patrice Chotard Add device tree bindings for the STM32 OSPI controller. Main features of the Octo-SPI controller : - support sNOR / sNAND / HyperRAM™ and HyperFlash™ devices. - Three functional modes: indirect, automatic-status polling, memory-mapped. - Up to 4 Gbytes of external memory can be addressed in indirect mode (per physical port and per CS), and up to 256 Mbytes in memory-mapped mode (combined for both physical ports and per CS). - Single-, dual-, quad-, and octal-SPI communication. - Dual-quad communication. - Single data rate (SDR) and double transfer rate (DTR). - Maximum target frequency is 133 MHz for SDR and 133 MHz for DTR. - Data strobe support. - DMA channel for indirect mode. - Double CS mapping that allows two external flash devices to be addressed with a single OCTOSPI controller mapped on a single OCTOSPI port. Signed-off-by: Patrice Chotard --- .../bindings/spi/st,stm32mp25-ospi.yaml | 102 ++++++++++++++++++ 1 file changed, 102 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/st,stm32mp25-ospi.yaml diff --git a/Documentation/devicetree/bindings/spi/st,stm32mp25-ospi.yaml b/Documentation/devicetree/bindings/spi/st,stm32mp25-ospi.yaml new file mode 100644 index 000000000000..f1d539444673 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/st,stm32mp25-ospi.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/st,stm32mp25-ospi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 Octal Serial Peripheral Interface (OSPI) + +maintainers: + - Patrice Chotard + +allOf: + - $ref: spi-controller.yaml# + +properties: + compatible: + const: st,stm32mp25-ospi + + reg: + maxItems: 1 + + memory-region: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + + resets: + items: + - description: phandle to OSPI block reset + - description: phandle to delay block reset + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + st,syscfg-dlyb: + description: phandle to syscon block + Use to set the OSPI delay block within syscon to + tune the phase of the RX sampling clock (or DQS) in order + to sample the data in their valid window and to + tune the phase of the TX launch clock in order to meet setup + and hold constraints of TX signals versus the memory clock. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + maxItems: 1 + + access-controllers: + description: phandle to the rifsc device to check access right + and in some cases, an additional phandle to the rcc device for + secure clock control + minItems: 1 + maxItems: 2 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + - st,syscfg-dlyb + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + spi@40430000 { + compatible = "st,stm32mp25-ospi"; + reg = <0x40430000 0x400>; + memory-region = <&mm_ospi1>; + interrupts = ; + dmas = <&hpdma 2 0x62 0x00003121 0x0>, + <&hpdma 2 0x42 0x00003112 0x0>; + dma-names = "tx", "rx"; + clocks = <&scmi_clk CK_SCMI_OSPI1>; + resets = <&scmi_reset RST_SCMI_OSPI1>, <&scmi_reset RST_SCMI_OSPI1DLL>; + access-controllers = <&rifsc 74>; + power-domains = <&CLUSTER_PD>; + st,syscfg-dlyb = <&syscfg 0x1000>; + + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + }; + };