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[83.97.153.254]) by smtp.gmail.com with ESMTPSA id eo9-20020a056000428900b00337d9b772c6sm1891773wrb.37.2024.01.26.11.47.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 11:47:16 -0800 (PST) Message-ID: Subject: [PATCH 3/3] spi: spi-rockchip: Fix unused chip select line when using gpio cs From: Luis de Arquer To: linux-spi@vger.kernel.org, linux-rockchip@lists.infradead.org Cc: broonie@kernel.org, heiko@sntech.de, linux-arm-kernel@lists.infradead.org, Robin Murphy , luis.dearquer@inertim.com Date: Fri, 26 Jan 2024 20:47:05 +0100 User-Agent: Evolution 3.44.4-0ubuntu2 Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Luis de Arquer This change allows the DT to use native c1 for a device while leaving native cs0 reserved for allowing gpio cs operation Signed-off-by: Luis de Arquer --- drivers/spi/spi-rockchip.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index e1ecd96c7858..e1ae62e8765c 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -247,13 +247,13 @@ static void rockchip_spi_set_cs(struct spi_device *spi, bool enable) pm_runtime_get_sync(rs->dev); if (spi_get_csgpiod(spi, 0)) - ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 1); + ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, ctlr->unused_native_cs); else ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi_get_chipselect(spi, 0))); } else { if (spi_get_csgpiod(spi, 0)) - ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 1); + ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, ctlr->unused_native_cs); else ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi_get_chipselect(spi, 0)));