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Fri, 6 Aug 2021 16:59:51 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; linux.intel.com; dkim=none (message not signed) header.d=none; linux.intel.com; dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT035.mail.protection.outlook.com (10.13.177.116) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4394.16 via Frontend Transport; Fri, 6 Aug 2021 16:59:51 +0000 Received: from sanjuamdntb2.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.12; Fri, 6 Aug 2021 11:59:48 -0500 From: Sanjay R Mehta To: , , , CC: , , , , Sanjay R Mehta Subject: [PATCH v3 1/4] thunderbolt: Add quirk to support vendor specific implementation Date: Fri, 6 Aug 2021 11:59:05 -0500 Message-ID: <1628269148-51355-2-git-send-email-Sanju.Mehta@amd.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1628269148-51355-1-git-send-email-Sanju.Mehta@amd.com> References: <1628269148-51355-1-git-send-email-Sanju.Mehta@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7bc6eb3f-2a14-46d1-039d-08d958fb9b8b X-MS-TrafficTypeDiagnostic: BL0PR12MB4705: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; 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CAT:NONE; SFS:(4636009)(346002)(376002)(39860400002)(396003)(136003)(36840700001)(46966006)(70586007)(336012)(2616005)(82310400003)(8676002)(426003)(70206006)(478600001)(5660300002)(36860700001)(356005)(47076005)(86362001)(7696005)(83380400001)(6666004)(81166007)(4326008)(2906002)(82740400003)(26005)(186003)(54906003)(8936002)(316002)(16526019)(110136005)(36756003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Aug 2021 16:59:51.8800 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7bc6eb3f-2a14-46d1-039d-08d958fb9b8b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT035.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4705 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Sanjay R Mehta Introduce nhi_check_quirks() routine to handle any vendor specific quirks to manage a hardware specific implementation. On Intel system, the USB4 controller requires the REG_DMA_MISC_INT_AUTO_CLEAR to be set. Hence handle it accordingly as per the USB4 specification via a quirk. Fixes: 046bee1f9ab8 ("thunderbolt: Add MSI-X support") Suggested-by: Mika Westerberg Signed-off-by: Basavaraj Natikar Signed-off-by: Sanjay R Mehta --- drivers/thunderbolt/nhi.c | 18 ++++++++++++++---- include/linux/thunderbolt.h | 1 + 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c index fa44332..7979638 100644 --- a/drivers/thunderbolt/nhi.c +++ b/drivers/thunderbolt/nhi.c @@ -43,6 +43,12 @@ static int ring_interrupt_index(struct tb_ring *ring) return bit; } +static void nhi_check_quirks(struct tb_nhi *nhi) +{ + if (nhi->pdev->vendor == PCI_VENDOR_ID_INTEL) + nhi->quirks |= REG_DMA_MISC_INT_AUTO_CLEAR; +} + /* * ring_interrupt_active() - activate/deactivate interrupts for a single ring * @@ -70,10 +76,12 @@ static void ring_interrupt_active(struct tb_ring *ring, bool active) * Ask the hardware to clear interrupt status bits automatically * since we already know which interrupt was triggered. */ - misc = ioread32(ring->nhi->iobase + REG_DMA_MISC); - if (!(misc & REG_DMA_MISC_INT_AUTO_CLEAR)) { - misc |= REG_DMA_MISC_INT_AUTO_CLEAR; - iowrite32(misc, ring->nhi->iobase + REG_DMA_MISC); + if (ring->nhi->quirks & REG_DMA_MISC_INT_AUTO_CLEAR) { + misc = ioread32(ring->nhi->iobase + REG_DMA_MISC); + if (!(misc & REG_DMA_MISC_INT_AUTO_CLEAR)) { + misc |= REG_DMA_MISC_INT_AUTO_CLEAR; + iowrite32(misc, ring->nhi->iobase + REG_DMA_MISC); + } } ivr_base = ring->nhi->iobase + REG_INT_VEC_ALLOC_BASE; @@ -1190,6 +1198,8 @@ static int nhi_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (!nhi->tx_rings || !nhi->rx_rings) return -ENOMEM; + nhi_check_quirks(nhi); + res = nhi_init_msi(nhi); if (res) { dev_err(&pdev->dev, "cannot enable MSI, aborting\n"); diff --git a/include/linux/thunderbolt.h b/include/linux/thunderbolt.h index e7c96c3..2144123 100644 --- a/include/linux/thunderbolt.h +++ b/include/linux/thunderbolt.h @@ -480,6 +480,7 @@ struct tb_nhi { bool going_away; struct work_struct interrupt_work; u32 hop_count; + u32 quirks; }; /**