From patchwork Mon Sep 21 02:44:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wan Ahmad Zainie X-Patchwork-Id: 297583 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CECA3C43465 for ; Mon, 21 Sep 2020 02:46:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8B93320665 for ; Mon, 21 Sep 2020 02:46:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726322AbgIUCqw (ORCPT ); Sun, 20 Sep 2020 22:46:52 -0400 Received: from mga09.intel.com ([134.134.136.24]:53124 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726104AbgIUCqw (ORCPT ); Sun, 20 Sep 2020 22:46:52 -0400 IronPort-SDR: yOdyzdiprVQC+zLCmN4zstBbB7bLeIGfef0BrRVjY837p/w2d1OuizNC6OMEO5ODF073aLHE89 2C6Uh+wvwOpQ== X-IronPort-AV: E=McAfee;i="6000,8403,9750"; a="161218608" X-IronPort-AV: E=Sophos;i="5.77,285,1596524400"; d="scan'208";a="161218608" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2020 19:46:51 -0700 IronPort-SDR: FiBfSDEGSN/WE2/QDHhi0DrZN2KbaYcMBohyKvv2QmJY8K/5unYu6xXEyK4t9MbrR7fqnI+u1f Q8URAWHuUOXA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,285,1596524400"; d="scan'208";a="321538153" Received: from wwanmoha-ilbpg2.png.intel.com ([10.88.227.42]) by orsmga002.jf.intel.com with ESMTP; 20 Sep 2020 19:46:48 -0700 From: Wan Ahmad Zainie To: kishon@ti.com, vkoul@kernel.org, robh+dt@kernel.org, balbi@kernel.org, gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, andriy.shevchenko@linux.intel.com, mgross@linux.intel.com, lakshmi.bai.raja.subramanian@intel.com, wan.ahmad.zainie.wan.mohamad@intel.com Subject: [PATCH 1/4] dt-bindings: phy: Add Intel Keem Bay USB PHY bindings Date: Mon, 21 Sep 2020 10:44:56 +0800 Message-Id: <20200921024459.20899-2-wan.ahmad.zainie.wan.mohamad@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200921024459.20899-1-wan.ahmad.zainie.wan.mohamad@intel.com> References: <20200921024459.20899-1-wan.ahmad.zainie.wan.mohamad@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Binding description for Intel Keem Bay USB PHY. Signed-off-by: Wan Ahmad Zainie --- .../bindings/phy/intel,phy-keembay-usb.yaml | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/intel,phy-keembay-usb.yaml diff --git a/Documentation/devicetree/bindings/phy/intel,phy-keembay-usb.yaml b/Documentation/devicetree/bindings/phy/intel,phy-keembay-usb.yaml new file mode 100644 index 000000000000..a217bb8ac5bc --- /dev/null +++ b/Documentation/devicetree/bindings/phy/intel,phy-keembay-usb.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/intel,phy-keembay-usb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Keem Bay USB PHY bindings + +maintainers: + - Wan Ahmad Zainie + +properties: + compatible: + const: intel,keembay-usb-phy + + reg: + items: + - description: USB APB CPR (clock, power, reset) register + - description: USB APB slave register + + reg-names: + items: + - const: cpr-apb-base + - const: slv-apb-base + + '#phy-cells': + const: 0 + +required: + - compatible + - reg + - '#phy-cells' + +additionalProperties: false + +examples: + - | + usb-phy@20400000 { + compatible = "intel,keembay-usb-phy"; + reg = <0x20400000 0x1c>, + <0x20480000 0xd0>; + reg-names = "cpr-apb-base", "slv-apb-base"; + #phy-cells = <0>; + };