From patchwork Tue Apr 13 07:36:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Petrosyan X-Patchwork-Id: 420605 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D470CC433ED for ; Tue, 13 Apr 2021 07:36:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B6D736135C for ; Tue, 13 Apr 2021 07:36:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240919AbhDMHhQ (ORCPT ); Tue, 13 Apr 2021 03:37:16 -0400 Received: from smtprelay-out1.synopsys.com ([149.117.73.133]:36492 "EHLO smtprelay-out1.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240890AbhDMHhP (ORCPT ); Tue, 13 Apr 2021 03:37:15 -0400 Received: from mailhost.synopsys.com (mdc-mailhost2.synopsys.com [10.225.0.210]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by smtprelay-out1.synopsys.com (Postfix) with ESMTPS id 5D6AE40162; Tue, 13 Apr 2021 07:36:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=synopsys.com; s=mail; t=1618299416; bh=8Wm8ArFTDkXMAZMgFkFQMI2XRAMfTrV/2W6Sg9JcQCs=; h=Date:In-Reply-To:References:From:Subject:To:Cc:From; b=jzhJyLzu+Kn9s+Gr7rk8yTQmW9xewZsssP+0tgHceDntnhrGmYZ1bVo51GrJoVfXq BZnjHc+Bw7jKWbSvcDahYw1ebY/mijsRUBWLZyg60GuK3Sm2VCSI2bLcw9qi5JKrtP bptuzk5TqWZbc16cZjcywAJGszKJN6X7gf3kb/jWimIEI2bvZhuqqvORSEPHmwScwh jWiRsyHLQUIDW4qpFLufzRi3epC1I8tLEQuS0hyGXisJHIxPv0HcH67ocNz6NOZv25 H0sRMxDzBDbBg2v95fScxhWeh4q4xfVQ4UKIPWlKDEisXeKxsyq1cFoq8/IOUUNxjT NU6qbvEbhdK+w== Received: from razpc-HP (razpc-hp.internal.synopsys.com [10.116.126.207]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailhost.synopsys.com (Postfix) with ESMTPSA id 9F493A0094; Tue, 13 Apr 2021 07:36:53 +0000 (UTC) Received: by razpc-HP (sSMTP sendmail emulation); Tue, 13 Apr 2021 11:36:52 +0400 Date: Tue, 13 Apr 2021 11:36:52 +0400 In-Reply-To: References: X-SNPS-Relay: synopsys.com From: Artur Petrosyan Subject: [PATCH v2 07/12] usb: dwc2: Update enter clock gating when port is suspended To: Felipe Balbi , Greg Kroah-Hartman , Minas Harutyunyan , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Cc: John Youn , Artur Petrosyan Message-Id: <20210413073653.9F493A0094@mailhost.synopsys.com> Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Updates the implementation of entering clock gating mode when core receives port suspend. Instead of setting the required bit fields of the registers inline, called the "dwc2_host_enter_clock_gating()" function. Signed-off-by: Artur Petrosyan --- Changes in v2: - None drivers/usb/dwc2/hcd.c | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c index 27f030d5de54..e1225fe6c61a 100644 --- a/drivers/usb/dwc2/hcd.c +++ b/drivers/usb/dwc2/hcd.c @@ -3298,7 +3298,6 @@ static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) { unsigned long flags; - u32 hprt0; u32 pcgctl; u32 gotgctl; int ret = 0; @@ -3323,22 +3322,12 @@ int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) break; case DWC2_POWER_DOWN_PARAM_HIBERNATION: case DWC2_POWER_DOWN_PARAM_NONE: - default: - hprt0 = dwc2_read_hprt0(hsotg); - hprt0 |= HPRT0_SUSP; - dwc2_writel(hsotg, hprt0, HPRT0); - hsotg->bus_suspended = true; /* - * If power_down is supported, Phy clock will be suspended - * after registers are backuped. + * If not hibernation nor partial power down are supported, + * clock gating is used to save power. */ - if (!hsotg->params.power_down) { - /* Suspend the Phy Clock */ - pcgctl = dwc2_readl(hsotg, PCGCTL); - pcgctl |= PCGCTL_STOPPCLK; - dwc2_writel(hsotg, pcgctl, PCGCTL); - udelay(10); - } + dwc2_host_enter_clock_gating(hsotg); + break; } /* For HNP the bus must be suspended for at least 200ms */