| Message ID | 20240911061720.495606-1-xu.yang_2@nxp.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v5,1/5] dt-bindings: phy: imx8mq-usb: add compatible "fsl,imx95-usb-phy" | expand |
On Wed, Sep 11, 2024 at 02:17:19PM +0800, Xu Yang wrote: > Add usb3 phy and controller nodes for imx95. > > Signed-off-by: Xu Yang <xu.yang_2@nxp.com> > > --- > Changes in v2: > - no changes > Changes in v3: > - no changes > Changes in v4: > - reorder nodes > Changes in v5: > - no changes > --- > arch/arm64/boot/dts/freescale/imx95.dtsi | 43 ++++++++++++++++++++++++ > 1 file changed, 43 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi > index 425272aa5a81..2377b3ade95a 100644 > --- a/arch/arm64/boot/dts/freescale/imx95.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi > @@ -1188,5 +1188,48 @@ pcie1_ep: pcie-ep@4c380000 { > power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; > status = "disabled"; > }; > + > + usb3: usb@4c010010 { Could this be added in order of unit-address? Shawn > + compatible = "fsl,imx95-dwc3", "fsl,imx8mp-dwc3"; > + reg = <0x0 0x4c010010 0x0 0x04>, > + <0x0 0x4c1f0000 0x0 0x20>; > + clocks = <&scmi_clk IMX95_CLK_HSIO>, > + <&scmi_clk IMX95_CLK_32K>; > + clock-names = "hsio", "suspend"; > + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; > + dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; > + status = "disabled"; > + > + usb3_dwc3: usb@4c100000 { > + compatible = "snps,dwc3"; > + reg = <0x0 0x4c100000 0x0 0x10000>; > + clocks = <&scmi_clk IMX95_CLK_HSIO>, > + <&scmi_clk IMX95_CLK_24M>, > + <&scmi_clk IMX95_CLK_32K>; > + clock-names = "bus_early", "ref", "suspend"; > + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; > + phys = <&usb3_phy>, <&usb3_phy>; > + phy-names = "usb2-phy", "usb3-phy"; > + snps,gfladj-refclk-lpm-sel-quirk; > + snps,parkmode-disable-ss-quirk; > + iommus = <&smmu 0xe>; > + }; > + }; > + > + usb3_phy: phy@4c1f0040 { > + compatible = "fsl,imx95-usb-phy", "fsl,imx8mp-usb-phy"; > + reg = <0x0 0x4c1f0040 0x0 0x40>, > + <0x0 0x4c1fc000 0x0 0x100>; > + clocks = <&scmi_clk IMX95_CLK_HSIO>; > + clock-names = "phy"; > + #phy-cells = <0>; > + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; > + orientation-switch; > + status = "disabled"; > + }; > }; > }; > -- > 2.34.1 >
Hi Shawn, On Wed, Oct 16, 2024 at 03:55:59PM +0800, Shawn Guo wrote: > On Wed, Sep 11, 2024 at 02:17:19PM +0800, Xu Yang wrote: > > Add usb3 phy and controller nodes for imx95. > > > > Signed-off-by: Xu Yang <xu.yang_2@nxp.com> > > > > --- > > Changes in v2: > > - no changes > > Changes in v3: > > - no changes > > Changes in v4: > > - reorder nodes > > Changes in v5: > > - no changes > > --- > > arch/arm64/boot/dts/freescale/imx95.dtsi | 43 ++++++++++++++++++++++++ > > 1 file changed, 43 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi > > index 425272aa5a81..2377b3ade95a 100644 > > --- a/arch/arm64/boot/dts/freescale/imx95.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi > > @@ -1188,5 +1188,48 @@ pcie1_ep: pcie-ep@4c380000 { > > power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; > > status = "disabled"; > > }; > > + > > + usb3: usb@4c010010 { > > Could this be added in order of unit-address? I've fixed such issue in v8: https://lore.kernel.org/linux-usb/20241015111018.2388913-2-xu.yang_2@nxp.com/ Thanks, Xu Yang
diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml index dc3a3f709fea..6d6d211883ae 100644 --- a/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml +++ b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml @@ -11,12 +11,17 @@ maintainers: properties: compatible: - enum: - - fsl,imx8mq-usb-phy - - fsl,imx8mp-usb-phy + oneOf: + - enum: + - fsl,imx8mq-usb-phy + - fsl,imx8mp-usb-phy + - items: + - const: fsl,imx95-usb-phy + - const: fsl,imx8mp-usb-phy reg: - maxItems: 1 + minItems: 1 + maxItems: 2 "#phy-cells": const: 0 @@ -89,7 +94,34 @@ required: - clocks - clock-names -additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx95-usb-phy + then: + properties: + reg: + items: + - description: USB PHY Control range + - description: USB PHY TCA Block range + else: + properties: + reg: + maxItems: 1 + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx95-usb-phy + then: + $ref: /schemas/usb/usb-switch.yaml# + +unevaluatedProperties: false examples: - |