From patchwork Mon Apr 28 07:38:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ze Huang X-Patchwork-Id: 886021 Received: from mail-m155101.qiye.163.com (mail-m155101.qiye.163.com [101.71.155.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B98611A3178; Mon, 28 Apr 2025 07:38:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=101.71.155.101 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745825919; cv=none; b=Qi8p4THLW9Co4e+pK7AtptMBYM3sZBPjyDT99XrSVpnTG+IKgPCfsqgwtpnKJ6X0nXCS1/WEgiA6RGm+eI+kjqAQTj3txiKORYRjZ3s6SyvP6VY4uxdbJCaijyXjLUB36qUXJczY5WBA4J3wweRzgmDBpibRAnLPOImpzHO77Zk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745825919; c=relaxed/simple; bh=CoIzsEZMyr39KazbVfZyOeCYt7jqNxYasrhcXgzRiw4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ErDUScjpnRb0BXKVfDSKBVjmybTt1InBJBoxVP718KtezR6tEU8s9J9lLPJqaA8ikcCmrajI1J3BG9os57jaP4Y8C6HEV73wIlQ7/J8Ix5+etj9cuLFWw3YW9PbVMJ0Ux2IsZ64dWfHaiMv/KB/FQI6dt4qcx0XOYHaaJ4jd7bI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=whut.edu.cn; spf=pass smtp.mailfrom=whut.edu.cn; arc=none smtp.client-ip=101.71.155.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=whut.edu.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=whut.edu.cn Received: from [127.0.0.1] (gy-adaptive-ssl-proxy-4-entmail-virt151.gy.ntes [27.18.99.221]) by smtp.qiye.163.com (Hmail) with ESMTP id 135f5a5ad; Mon, 28 Apr 2025 15:38:23 +0800 (GMT+08:00) From: Ze Huang Date: Mon, 28 Apr 2025 15:38:11 +0800 Subject: [PATCH 1/2] dt-bindings: usb: dwc3: add support for SpacemiT K1 Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250428-b4-k1-dwc3-v2-v1-1-7cb061abd619@whut.edu.cn> References: <20250428-b4-k1-dwc3-v2-v1-0-7cb061abd619@whut.edu.cn> In-Reply-To: <20250428-b4-k1-dwc3-v2-v1-0-7cb061abd619@whut.edu.cn> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, Ze Huang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1745825898; l=3090; i=huangze@whut.edu.cn; s=20250325; h=from:subject:message-id; bh=CoIzsEZMyr39KazbVfZyOeCYt7jqNxYasrhcXgzRiw4=; b=VafuAbLYli3pLw7uTELkEWZhH9nZF4oxDPYqog6wNcJ/qkjnoib83skFt6u+36RbW6MV0XFTZ t2c4+FrBmEEBkbMc/VRWy173JhQl4W2c2DjlpU14exHyIU01l36kPzX X-Developer-Key: i=huangze@whut.edu.cn; a=ed25519; pk=C3zfn/kH6oMJickaXBa8dxTZO68EBiD93F+tAenboRA= X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlDTE9PVkpNTElIQ04ZHUgfQ1YeHw5VEwETFhoSFy QUDg9ZV1kYEgtZQVlJTFVKQ1VCQlVJSUpZV1kWGg8SFR0UWUFZT0tIVUpLSEpOTE5VSktLVUpCS0 tZBg++ X-HM-Tid: 0a967b55360e03a1kunm135f5a5ad X-HM-MType: 10 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6NzI6ASo*DjIBFTU0HyIvAUJL MjgaCxpVSlVKTE9OQ0lOQktCT0NPVTMWGhIXVRMOGhUcAR47DBMOD1UeHw5VGBVFWVdZEgtZQVlJ TFVKQ1VCQlVJSUpZV1kIAVlBT05JTzcG Add support for the USB 3.0 Dual-Role Device (DRD) controller embedded in the SpacemiT K1 SoC. The controller is based on the Synopsys DesignWare Core USB 3 (DWC3) IP, supporting both Host and Device modes for USB 3.0 and USB 2.0 standards. Signed-off-by: Ze Huang --- .../devicetree/bindings/usb/spacemit,k1-dwc3.yaml | 95 ++++++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml new file mode 100644 index 0000000000000000000000000000000000000000..5aece388900fa5bda9acb19add658310064bef8f --- /dev/null +++ b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/spacemit,k1-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 SuperSpeed DWC3 USB SoC Controller + +maintainers: + - Ze Huang + +description: | + The SpacemiT K1 embeds a DWC3 USB IP Core which supports both Host and Device + functions for USB 3.0 and USB 2.0 standards. + + Key features: + - USB3.0 SuperSpeed and USB2.0 High/Full/Low-Speed support + - Supports low-power modes (USB2.0 suspend, USB3.0 U1/U2/U3) + - Internal DMA controller and flexible endpoint FIFO sizing + + Communication Interface: + - Use of PIPE3 (125MHz) interface for USB3.0 PHY + - Use of UTMI+ (30/60MHz) interface for USB2.0 PHY + + The common content of the node is defined in snps,dwc3.yaml. + +select: + properties: + compatible: + contains: + enum: + - spacemit,k1-dwc3 + required: + - compatible + +properties: + compatible: + items: + - enum: + - spacemit,k1-dwc3 + - const: snps,dwc3 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: bus_early + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interconnects: + maxItems: 1 + description: + On SpacemiT K1, USB performs DMA through bus other than parent DT node. + The 'interconnects' property explicitly describes this path, ensuring + correct address translation. + + interconnect-names: + const: dma-mem + + vbus-supply: + description: A phandle to the regulator supplying the VBUS voltage. + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - interrupts + - interconnects + - interconnect-names + +additionalProperties: false + +examples: + - | + usb@c0a00000 { + compatible = "spacemit,k1-dwc3", "snps,dwc3"; + reg = <0xc0a00000 0x10000>; + clocks = <&syscon_apmu 16>; + clock-names = "bus_early"; + resets = <&syscon_apmu 8>; + interrupt-parent = <&plic>; + interrupts = <125>; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + };