@@ -3083,14 +3083,14 @@ void xhci_update_erst_dequeue(struct xhci_hcd *xhci,
static void xhci_clear_interrupt_pending(struct xhci_interrupter *ir)
{
if (!ir->ip_autoclear) {
- u32 irq_pending;
+ u32 iman;
- irq_pending = readl(&ir->ir_set->irq_pending);
- irq_pending |= IMAN_IP;
- writel(irq_pending, &ir->ir_set->irq_pending);
+ iman = readl(&ir->ir_set->iman);
+ iman |= IMAN_IP;
+ writel(iman, &ir->ir_set->iman);
/* Read operation to guarantee the write has been flushed from posted buffers */
- readl(&ir->ir_set->irq_pending);
+ readl(&ir->ir_set->iman);
}
}
@@ -330,12 +330,12 @@ int xhci_enable_interrupter(struct xhci_interrupter *ir)
if (!ir || !ir->ir_set)
return -EINVAL;
- iman = readl(&ir->ir_set->irq_pending);
+ iman = readl(&ir->ir_set->iman);
iman |= IMAN_IE;
- writel(iman, &ir->ir_set->irq_pending);
+ writel(iman, &ir->ir_set->iman);
/* Read operation to guarantee the write has been flushed from posted buffers */
- readl(&ir->ir_set->irq_pending);
+ readl(&ir->ir_set->iman);
return 0;
}
@@ -346,11 +346,11 @@ int xhci_disable_interrupter(struct xhci_hcd *xhci, struct xhci_interrupter *ir)
if (!ir || !ir->ir_set)
return -EINVAL;
- iman = readl(&ir->ir_set->irq_pending);
+ iman = readl(&ir->ir_set->iman);
iman &= ~IMAN_IE;
- writel(iman, &ir->ir_set->irq_pending);
+ writel(iman, &ir->ir_set->iman);
- iman = readl(&ir->ir_set->irq_pending);
+ iman = readl(&ir->ir_set->iman);
if (iman & IMAN_IP)
xhci_dbg(xhci, "%s: Interrupt pending\n", __func__);
@@ -834,7 +834,7 @@ static void xhci_save_registers(struct xhci_hcd *xhci)
ir->s3_erst_size = readl(&ir->ir_set->erst_size);
ir->s3_erst_base = xhci_read_64(xhci, &ir->ir_set->erst_base);
ir->s3_erst_dequeue = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
- ir->s3_irq_pending = readl(&ir->ir_set->irq_pending);
+ ir->s3_iman = readl(&ir->ir_set->iman);
ir->s3_irq_control = readl(&ir->ir_set->irq_control);
}
}
@@ -858,7 +858,7 @@ static void xhci_restore_registers(struct xhci_hcd *xhci)
writel(ir->s3_erst_size, &ir->ir_set->erst_size);
xhci_write_64(xhci, ir->s3_erst_base, &ir->ir_set->erst_base);
xhci_write_64(xhci, ir->s3_erst_dequeue, &ir->ir_set->erst_dequeue);
- writel(ir->s3_irq_pending, &ir->ir_set->irq_pending);
+ writel(ir->s3_iman, &ir->ir_set->iman);
writel(ir->s3_irq_control, &ir->ir_set->irq_control);
}
}
@@ -211,7 +211,7 @@ struct xhci_op_regs {
/**
* struct xhci_intr_reg - Interrupt Register Set, v1.2 section 5.5.2.
- * @irq_pending: IMAN - Interrupt Management Register. Used to enable
+ * @iman: IMAN - Interrupt Management Register. Used to enable
* interrupts and check for pending interrupts.
* @irq_control: IMOD - Interrupt Moderation Register. Used to throttle interrupts.
* @erst_size: ERSTSZ - Number of segments in the Event Ring Segment Table (ERST).
@@ -226,7 +226,7 @@ struct xhci_op_regs {
* updates the dequeue pointer.
*/
struct xhci_intr_reg {
- __le32 irq_pending;
+ __le32 iman;
__le32 irq_control;
__le32 erst_size;
__le32 rsvd;
@@ -234,7 +234,7 @@ struct xhci_intr_reg {
__le64 erst_dequeue;
};
-/* irq_pending bitmasks */
+/* iman bitmasks */
/* bit 0 - Interrupt Pending (IP), whether there is an interrupt pending. Write-1-to-clear. */
#define IMAN_IP (1 << 0)
/* bit 1 - Interrupt Enable (IE), whether the interrupter is capable of generating an interrupt */
@@ -1452,7 +1452,7 @@ struct xhci_interrupter {
bool ip_autoclear;
u32 isoc_bei_interval;
/* For interrupter registers save and restore over suspend/resume */
- u32 s3_irq_pending;
+ u32 s3_iman;
u32 s3_irq_control;
u32 s3_erst_size;
u64 s3_erst_base;