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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id o3-20020a5d6843000000b003095a329e90sm945809wrw.97.2023.05.25.01.34.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 01:34:01 -0700 (PDT) From: Alexandre Mergnat Date: Thu, 25 May 2023 10:33:16 +0200 Subject: [PATCH v8 07/10] arm64: dts: mediatek: add ethernet support for mt8365-evk MIME-Version: 1.0 Message-Id: <20230203-evk-board-support-v8-7-7019f3fd0adf@baylibre.com> References: <20230203-evk-board-support-v8-0-7019f3fd0adf@baylibre.com> In-Reply-To: <20230203-evk-board-support-v8-0-7019f3fd0adf@baylibre.com> To: Catalin Marinas , Will Deacon , Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno , Conor Dooley Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, Alexandre Mergnat , Kevin Hilman X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2249; i=amergnat@baylibre.com; h=from:subject:message-id; bh=U+Xs+VxtYFwUGhR18YiqTjcMEMzYJRNse3ci95tZvgA=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBkbx1vMkOP5L8x//cPNHtpPDsMNnba4MKariCWnjnC vFJk/COJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZG8dbwAKCRArRkmdfjHURSTIEA CnP+Sp9PCcyYKQpGswvuSybT/Qu8Ldh8ib2w+5v/Fg2qP3mNArkJ4dKp3xkQ18OFAaC9tD4Mg2+JRp tN6kVnrVQXzOaYLAdLU84jZ/c2+/QKWklrvL3L3tWx+RaCQPzulHag0DnOByHmI4wDLRCYxHhpFKQM GPEhXcf4rcqWPqDx7mk5552FDu2YHLIkIajwh//clAKRFU/KixwanPXGooo253UVaHSgKFssZ+onro 4vvzA15OFWR6YvK7H7G5J3buTpMyMUgM6nNK+sZMAYBB7rmnKlDPkjWUmSk0QPq/93AHB9Bw04Dxgl 71xi9vsNEm0bLA9rnmg/SnsY84PJ7JyyYK4yUiBSDlVpT25J9n8pY+usn3e4Kjm8OXW8tp/VILWDVL 4eiUaZ17+eGfxQ+G8drgeY0zySuTzBTBiYOzWsh1JauL02zjs9xMqSB7LAK+OObR7jzw09pF4ggFek bSD7MrHt5le9WKbs6SDOC1NNb3DbFQJRgQfj1p+mVTz0PDoEDV0N0BLL3/w80RtXTfvjq53qa3//7q ZISN8IzDUKu+TxO8/ikTSaoEfT6E+Ni4y6TtnIbdB23vtTIrVyFPgt4QhtuaXS0P1F/kzs2NE5WKnT b5DhDcy34NN1+b1Jr5ESIteKC8eATq/40dGIet6Pr+cuDuePJnv97wA6zy1A== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org - Enable "vibr" and "vsim2" regulators to power the ethernet chip. Tested-by: Kevin Hilman Signed-off-by: Alexandre Mergnat Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 48 +++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts index 1a5769c397c2..86524cbf4354 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -88,6 +88,29 @@ optee_reserved: optee@43200000 { }; }; +ðernet { + pinctrl-0 = <ðernet_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy>; + phy-mode = "rmii"; + /* + * Ethernet and HDMI (DSI0) are sharing pins. + * Only one can be enabled at a time and require the physical switch + * SW2101 to be set on LAN position + * mt6357_vibr_reg and mt6357_vsim2_reg are needed to supply ethernet + */ + status = "disabled"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + eth_phy: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + &i2c0 { clock-frequency = <100000>; pinctrl-0 = <&i2c0_pins>; @@ -138,6 +161,31 @@ &mt6357_pmic { }; &pio { + ethernet_pins: ethernet-pins { + phy_reset_pins { + pinmux = ; + }; + + rmii_pins { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + gpio_keys: gpio-keys-pins { pins { pinmux = ;