From patchwork Wed Mar 8 03:40:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xingyu Wu X-Patchwork-Id: 661606 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4973C6FA99 for ; Wed, 8 Mar 2023 03:41:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229972AbjCHDlM convert rfc822-to-8bit (ORCPT ); Tue, 7 Mar 2023 22:41:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43238 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229901AbjCHDkt (ORCPT ); Tue, 7 Mar 2023 22:40:49 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E408296C1F; Tue, 7 Mar 2023 19:40:44 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 9B47A24E1D2; Wed, 8 Mar 2023 11:40:38 +0800 (CST) Received: from EXMBX061.cuchost.com (172.16.6.61) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 8 Mar 2023 11:40:38 +0800 Received: from localhost.localdomain (183.27.97.46) by EXMBX061.cuchost.com (172.16.6.61) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 8 Mar 2023 11:40:37 +0800 From: Xingyu Wu To: , , , Wim Van Sebroeck , Guenter Roeck , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley CC: Rob Herring , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Xingyu Wu , Samin Guo , Subject: [PATCH v4 1/3] dt-bindings: watchdog: Add watchdog for StarFive JH7100 and JH7110 Date: Wed, 8 Mar 2023 11:40:34 +0800 Message-ID: <20230308034036.99213-2-xingyu.wu@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230308034036.99213-1-xingyu.wu@starfivetech.com> References: <20230308034036.99213-1-xingyu.wu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.46] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX061.cuchost.com (172.16.6.61) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org Add bindings to describe the watchdog for the StarFive JH7100/JH7110 SoC. And Use JH7100 as first StarFive SoC with watchdog. Signed-off-by: Xingyu Wu --- .../watchdog/starfive,jh7100-wdt.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/starfive,jh7100-wdt.yaml diff --git a/Documentation/devicetree/bindings/watchdog/starfive,jh7100-wdt.yaml b/Documentation/devicetree/bindings/watchdog/starfive,jh7100-wdt.yaml new file mode 100644 index 000000000000..68f3f6fd08a6 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/starfive,jh7100-wdt.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/starfive,jh7100-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive Watchdog for JH7100 and JH7110 SoC + +maintainers: + - Xingyu Wu + - Samin Guo + +description: + The JH7100 and JH7110 watchdog both are 32 bit counters. JH7100 watchdog + has only one timeout phase and reboots. And JH7110 watchdog has two + timeout phases. At the first phase, the signal of watchdog interrupt + output(WDOGINT) will rise when counter is 0. The counter will reload + the timeout value. And then, if counter decreases to 0 again and WDOGINT + isn't cleared, the watchdog will reset the system unless the watchdog + reset is disabled. + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + enum: + - starfive,jh7100-wdt + - starfive,jh7110-wdt + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: APB clock + - description: Core clock + + clock-names: + items: + - const: apb + - const: core + + resets: + items: + - description: APB reset + - description: Core reset + +required: + - compatible + - reg + - clocks + - clock-names + - resets + +unevaluatedProperties: false + +examples: + - | + watchdog@12480000 { + compatible = "starfive,jh7100-wdt"; + reg = <0x12480000 0x10000>; + clocks = <&clk 171>, + <&clk 172>; + clock-names = "apb", "core"; + resets = <&rst 99>, + <&rst 100>; + };