From patchwork Fri Feb 7 21:30:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer_via_B4_Relay?= X-Patchwork-Id: 863265 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C9A51DE2B5; Fri, 7 Feb 2025 21:30:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738963837; cv=none; b=iivGuvTk89NgEw2mQX1CqFIg02FtozmMyzK8I+DCuIlbxo2t8Nt30p0sKQ58Kii42tmyak17nuoB9Mt+UulvJe4051ixFNRJY6lO5K+YvYROsVb+SG/TpBOVCXG5mM0yktjVV/EzuBSgCnr/9thErmgDWVySM6bA5Fwuq9G0KYI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738963837; c=relaxed/simple; bh=9PfartHueaGr5g/oiEQ4N02BOdiK1bkzjtmyOp5ecwc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nxde4EZtpkrE29nyWiJtRCzuxBOgKWj6hOxd69Xefm9cnEYtcZqvKMksCkuofu4F7QPYey53H2HC2BEBjMed3NbkZ5RxIpLeqjRfSt63USpacb4G+4MhA9Rp8cPXou6Cw69sgZyAjATTf43Y4KMZHDZ/UoLYn8i75pWyOj8hFMI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XSQHX1P/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XSQHX1P/" Received: by smtp.kernel.org (Postfix) with ESMTPS id D0E9BC2BCAF; Fri, 7 Feb 2025 21:30:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738963835; bh=9PfartHueaGr5g/oiEQ4N02BOdiK1bkzjtmyOp5ecwc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=XSQHX1P/S2G1qfpQ/lXzX+rfcRzNCc7YQw1t5fQx/FBgV+6eHzOT1kZEdBWqpqcly 73zaH8p3WSTU8UjGDULSrGjSDdK/Rf+GGnTH4uFRAD7/j70M6M2AankYYiGMYbBSMM cgr4PIqZniKAB6xga3cp41m4GXZxSwIibQDUGj5+kfDLg2rf30/ItfSa8vcj7chlmC 2StvUoQuTlhv8p7j595JyvCQvdqOAvjNkLKrSx2gm+76GA2Rv97LRFxqUXo8CCiNGE blO3mYTf427SgHgvEjwxnLwC1wLoEq/6Gfq98VlpqbWunDNMJT7FxQwud840BYV2ds 1SfseSF+JAEJw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4E86C021A0; Fri, 7 Feb 2025 21:30:35 +0000 (UTC) From: =?utf-8?q?J=2E_Neusch=C3=A4fer_via_B4_Relay?= Date: Fri, 07 Feb 2025 22:30:24 +0100 Subject: [PATCH v2 07/12] dt-bindings: watchdog: Convert mpc8xxx-wdt to YAML Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250207-ppcyaml-v2-7-8137b0c42526@posteo.net> References: <20250207-ppcyaml-v2-0-8137b0c42526@posteo.net> In-Reply-To: <20250207-ppcyaml-v2-0-8137b0c42526@posteo.net> To: devicetree@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, Krzysztof Kozlowski Cc: imx@lists.linux.dev, Scott Wood , Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , Christophe Leroy , Naveen N Rao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Damien Le Moal , Niklas Cassel , Herbert Xu , "David S. Miller" , Lee Jones , Vinod Koul , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Helgaas , =?utf-8?q?J=2E_Neusch=C3=A4fer?= , Wim Van Sebroeck , Guenter Roeck , Mark Brown , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , linux-kernel@vger.kernel.org, linux-ide@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-pci@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org, =?utf-8?q?J=2E_N?= =?utf-8?q?eusch=C3=A4fer?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1738963832; l=3875; i=j.ne@posteo.net; s=20240329; h=from:subject:message-id; bh=IzmYTjKFSaMe8r78V7lDGgTUX3OYdgsgRQLqgb3+W5E=; b=TIcbvGAq3Pd5vRP/+yayQPTA4eKxHfJJoBevDPlnNqk/TGLY/RAUlfbrPChXuI2XTMp9PTJ3j xT5C+X1jArUDzNFPHWmc4Z83M+LYPrzacfBFMNuxejNmMMtEVUUSfdW X-Developer-Key: i=j.ne@posteo.net; a=ed25519; pk=NIe0bK42wNaX/C4bi6ezm7NJK0IQE+8MKBm7igFMIS4= X-Endpoint-Received: by B4 Relay for j.ne@posteo.net/20240329 with auth_id=156 X-Original-From: =?utf-8?q?J=2E_Neusch=C3=A4fer?= Reply-To: j.ne@posteo.net From: "J. Neuschäfer" Convert mpc83xx-wdt.txt to YAML to enable automatic schema validation. Reviewed-by: Rob Herring (Arm) Signed-off-by: J. Neuschäfer --- V2: - trim subject line (remove "binding") - fix property order to comply with dts coding style --- .../devicetree/bindings/watchdog/mpc8xxx-wdt.txt | 25 --------- .../devicetree/bindings/watchdog/mpc8xxx-wdt.yaml | 64 ++++++++++++++++++++++ 2 files changed, 64 insertions(+), 25 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/mpc8xxx-wdt.txt b/Documentation/devicetree/bindings/watchdog/mpc8xxx-wdt.txt deleted file mode 100644 index a384ff5b3ce8c62d813fc23d72f74e2158ff543e..0000000000000000000000000000000000000000 --- a/Documentation/devicetree/bindings/watchdog/mpc8xxx-wdt.txt +++ /dev/null @@ -1,25 +0,0 @@ -* Freescale mpc8xxx watchdog driver (For 83xx, 86xx and 8xx) - -Required properties: -- compatible: Shall contain one of the following: - "mpc83xx_wdt" for an mpc83xx - "fsl,mpc8610-wdt" for an mpc86xx - "fsl,mpc823-wdt" for an mpc8xx -- reg: base physical address and length of the area hosting the - watchdog registers. - On the 83xx, "Watchdog Timer Registers" area: <0x200 0x100> - On the 86xx, "Watchdog Timer Registers" area: <0xe4000 0x100> - On the 8xx, "General System Interface Unit" area: <0x0 0x10> - -Optional properties: -- reg: additional physical address and length (4) of location of the - Reset Status Register (called RSTRSCR on the mpc86xx) - On the 83xx, it is located at offset 0x910 - On the 86xx, it is located at offset 0xe0094 - On the 8xx, it is located at offset 0x288 - -Example: - WDT: watchdog@0 { - compatible = "fsl,mpc823-wdt"; - reg = <0x0 0x10 0x288 0x4>; - }; diff --git a/Documentation/devicetree/bindings/watchdog/mpc8xxx-wdt.yaml b/Documentation/devicetree/bindings/watchdog/mpc8xxx-wdt.yaml new file mode 100644 index 0000000000000000000000000000000000000000..09e6dcf5bf186e4d15ee84f03ce64dd53155198d --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/mpc8xxx-wdt.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/mpc8xxx-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale MPC8xxx watchdog timer (For 83xx, 86xx and 8xx) + +maintainers: + - J. Neuschäfer + +properties: + compatible: + enum: + - mpc83xx_wdt # for an mpc83xx + - fsl,mpc8610-wdt # for an mpc86xx + - fsl,mpc823-wdt # for an mpc8xx + + device_type: + const: watchdog + + reg: + minItems: 1 + items: + - description: | + Base physical address and length of the area hosting the watchdog + registers. + + On the 83xx, "Watchdog Timer Registers" area: <0x200 0x100> + On the 86xx, "Watchdog Timer Registers" area: <0xe4000 0x100> + On the 8xx, "General System Interface Unit" area: <0x0 0x10> + + - description: | + Additional optional physical address and length (4) of location of + the Reset Status Register (called RSTRSCR on the mpc86xx) + + On the 83xx, it is located at offset 0x910 + On the 86xx, it is located at offset 0xe0094 + On the 8xx, it is located at offset 0x288 + +required: + - compatible + - reg + +allOf: + - $ref: watchdog.yaml# + +additionalProperties: false + +examples: + - | + WDT: watchdog@0 { + compatible = "fsl,mpc823-wdt"; + reg = <0x0 0x10 0x288 0x4>; + }; + + - | + wdt: watchdog@200 { + compatible = "mpc83xx_wdt"; + reg = <0x200 0x100>; + device_type = "watchdog"; + }; + +...