From patchwork Thu Oct 8 11:28:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shayne Chen X-Patchwork-Id: 268844 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.1 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83B54C4363A for ; Thu, 8 Oct 2020 11:33:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2A7652145D for ; Thu, 8 Oct 2020 11:33:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="i8er5Bm4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729440AbgJHLdV (ORCPT ); Thu, 8 Oct 2020 07:33:21 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:33947 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729371AbgJHLdU (ORCPT ); Thu, 8 Oct 2020 07:33:20 -0400 X-UUID: 7703e1a59818488b97e8e9f06925a20d-20201008 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=lB2yOL1yHNpt3oHBOa9YeTNVGOoIXY9o4YvJcmDEOSo=; b=i8er5Bm4u3Nu6JJFAY2mNnNMKf6YabRwkwPJvB8mhiQnIJ5petOEbbklNeTZUUH+Yd6zBEKjuvWR7JsCXjeK5kyylWlNyBvW9oagkJEV+l5+kshiLNfIdVxCqcIIU88zc0MqvqE22N67ckCHO0xs0mYuHKwFlqc/3xSohEjC6Ko=; X-UUID: 7703e1a59818488b97e8e9f06925a20d-20201008 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1490517639; Thu, 08 Oct 2020 19:33:15 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 8 Oct 2020 19:33:13 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 8 Oct 2020 19:33:13 +0800 From: Shayne Chen To: Felix Fietkau CC: linux-wireless , Lorenzo Bianconi , Ryder Lee , Evelyn Tsai , linux-mediatek , Shayne Chen Subject: [PATCH 05/10] mt76: mt7915: fix tx rate related fields in tx descriptor Date: Thu, 8 Oct 2020 19:28:59 +0800 Message-ID: <20201008112904.10620-5-shayne.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20201008112904.10620-1-shayne.chen@mediatek.com> References: <20201008112904.10620-1-shayne.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org Correct the bitfields of tx rateval and bw in tx descriptor. Signed-off-by: Shayne Chen Reviewed-by: Ryder Lee --- drivers/net/wireless/mediatek/mt76/mt7915/mac.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.h b/drivers/net/wireless/mediatek/mt76/mt7915/mac.h index 456bb81..0921b6f 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.h +++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.h @@ -231,7 +231,7 @@ enum tx_mcu_port_q_idx { #define MT_TXD6_ANT_ID GENMASK(7, 4) #define MT_TXD6_DYN_BW BIT(3) #define MT_TXD6_FIXED_BW BIT(2) -#define MT_TXD6_BW GENMASK(2, 0) +#define MT_TXD6_BW GENMASK(1, 0) #define MT_TXD7_TXD_LEN GENMASK(31, 30) #define MT_TXD7_UDP_TCP_SUM BIT(29) @@ -248,7 +248,9 @@ enum tx_mcu_port_q_idx { #define MT_TX_RATE_STBC BIT(13) #define MT_TX_RATE_NSS GENMASK(12, 10) #define MT_TX_RATE_MODE GENMASK(9, 6) -#define MT_TX_RATE_IDX GENMASK(5, 0) +#define MT_TX_RATE_SU_EXT_TONE BIT(5) +#define MT_TX_RATE_DCM BIT(4) +#define MT_TX_RATE_IDX GENMASK(3, 0) #define MT_TXP_MAX_BUF_NUM 6