@@ -287,7 +287,7 @@ int iwl_trans_pcie_ctx_info_gen3_load_pnvm(struct iwl_trans *trans,
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl =
&trans_pcie->prph_scratch->ctrl_cfg;
- struct iwl_dram_data *dram = &trans_pcie->pnvm_dram;
+ struct iwl_dram_data *dram = &trans_pcie->pnvm_dram[0];
u32 len, len0, len1;
if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
@@ -324,6 +324,7 @@ int iwl_trans_pcie_ctx_info_gen3_load_pnvm(struct iwl_trans *trans,
dram->size = len;
memcpy(dram->block, pnvm_payloads->chunks[0].data, len0);
memcpy((u8 *)dram->block + len0, pnvm_payloads->chunks[1].data, len1);
+ trans_pcie->n_pnvm_regions = 1;
trans->pnvm_loaded = true;
return 0;
@@ -337,11 +338,15 @@ void iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans)
if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
return;
-
+ /* FIXME: currently we concatenate payloads and save them only in
+ * pnvm_dram[0] - therefor only pnvm_dram[0] is delivered to the
+ * prph_sc. Need to add a UCODE sensitivity and another case in which
+ * we deliver to the prph_sc an array with all the DRAM addresses.
+ */
prph_sc_ctrl->pnvm_cfg.pnvm_base_addr =
- cpu_to_le64(trans_pcie->pnvm_dram.physical);
+ cpu_to_le64(trans_pcie->pnvm_dram[0].physical);
prph_sc_ctrl->pnvm_cfg.pnvm_size =
- cpu_to_le32(trans_pcie->pnvm_dram.size);
+ cpu_to_le32(trans_pcie->pnvm_dram[0].size);
}
@@ -23,6 +23,7 @@
#include "iwl-op-mode.h"
#include "iwl-drv.h"
#include "queue/tx.h"
+#include "iwl-context-info.h"
/*
* RX related structures and functions
@@ -306,7 +307,8 @@ enum iwl_pcie_imr_status {
* @trans: pointer to the generic transport area
* @scd_base_addr: scheduler sram base address in SRAM
* @kw: keep warm address
- * @pnvm_dram: DRAM area that contains the PNVM data
+ * @pnvm_dram: array of several DRAM areas that contains the PNVM data
+ * @n_pnvm_regions: number of DRAM regions that were allocated for the pnvm
* @pci_dev: basic pci-network driver stuff
* @hw_base: pci hardware address support
* @ucode_write_complete: indicates that the ucode has been copied.
@@ -380,7 +382,9 @@ struct iwl_trans_pcie {
u32 scd_base_addr;
struct iwl_dma_ptr kw;
- struct iwl_dram_data pnvm_dram;
+ /* pnvm data */
+ struct iwl_dram_data pnvm_dram[IPC_DRAM_MAP_ENTRY_NUM_MAX];
+ u8 n_pnvm_regions;
struct iwl_dram_data reduce_power_dram;
struct iwl_txq *txq_memory;
@@ -478,6 +482,8 @@ struct iwl_trans
const struct pci_device_id *ent,
const struct iwl_cfg_trans_params *cfg_trans);
void iwl_trans_pcie_free(struct iwl_trans *trans);
+void iwl_trans_pcie_free_pnvm_dram(struct iwl_trans_pcie *trans_pcie,
+ struct device *dev);
bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans);
#define _iwl_trans_pcie_grab_nic_access(trans) \
@@ -1993,6 +1993,19 @@ static void iwl_trans_pcie_configure(struct iwl_trans *trans,
trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake;
}
+void iwl_trans_pcie_free_pnvm_dram(struct iwl_trans_pcie *trans_pcie,
+ struct device *dev)
+{
+ u8 i;
+
+ for (i = 0; i < trans_pcie->n_pnvm_regions; i++) {
+ dma_free_coherent(dev, trans_pcie->pnvm_dram[i].size,
+ trans_pcie->pnvm_dram[i].block,
+ trans_pcie->pnvm_dram[i].physical);
+ }
+ trans_pcie->n_pnvm_regions = 0;
+}
+
void iwl_trans_pcie_free(struct iwl_trans *trans)
{
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
@@ -2025,10 +2038,7 @@ void iwl_trans_pcie_free(struct iwl_trans *trans)
iwl_pcie_free_fw_monitor(trans);
- if (trans_pcie->pnvm_dram.size)
- dma_free_coherent(trans->dev, trans_pcie->pnvm_dram.size,
- trans_pcie->pnvm_dram.block,
- trans_pcie->pnvm_dram.physical);
+ iwl_trans_pcie_free_pnvm_dram(trans_pcie, trans->dev);
if (trans_pcie->reduce_power_dram.size)
dma_free_coherent(trans->dev,