@@ -3341,6 +3341,10 @@ struct rtw89_dig_regs {
u32 seg0_pd_reg;
u32 pd_lower_bound_mask;
u32 pd_spatial_reuse_en;
+ u32 bmode_pd_reg;
+ u32 bmode_cca_rssi_limit_en;
+ u32 bmode_pd_lower_bound_reg;
+ u32 bmode_rssi_nocca_low_th_mask;
struct rtw89_reg_def p0_lna_init;
struct rtw89_reg_def p1_lna_init;
struct rtw89_reg_def p0_tia_init;
@@ -3230,7 +3230,9 @@ static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx)
static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev)
{
+ const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
+ const struct rtw89_ccx_regs *ccx = phy->ccx;
env->ccx_manual_ctrl = false;
env->ccx_ongoing = false;
@@ -3238,10 +3240,10 @@ static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev)
env->ccx_period = 0;
env->ccx_unit_idx = RTW89_CCX_32_US;
- rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EN_MSK, 1);
- rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_TRIG_OPT_MSK, 1);
- rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1);
- rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EDCCA_OPT_MSK,
+ rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->en_mask, 1);
+ rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->trig_opt_mask, 1);
+ rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1);
+ rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->edcca_opt_mask,
RTW89_CCX_EDCCA_BW20_0);
}
@@ -3356,25 +3358,27 @@ static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev,
static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev)
{
+ const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
+ const struct rtw89_ccx_regs *ccx = phy->ccx;
u8 i = 0;
- rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_LOW_MSK,
+ rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_l_mask,
env->ifs_clm_th_l[0]);
- rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_LOW_MSK,
+ rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_l_mask,
env->ifs_clm_th_l[1]);
- rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_LOW_MSK,
+ rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_l_mask,
env->ifs_clm_th_l[2]);
- rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_LOW_MSK,
+ rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_l_mask,
env->ifs_clm_th_l[3]);
- rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_HIGH_MSK,
+ rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_h_mask,
env->ifs_clm_th_h[0]);
- rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_HIGH_MSK,
+ rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_h_mask,
env->ifs_clm_th_h[1]);
- rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_HIGH_MSK,
+ rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_h_mask,
env->ifs_clm_th_h[2]);
- rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_HIGH_MSK,
+ rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_h_mask,
env->ifs_clm_th_h[3]);
for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
@@ -3385,7 +3389,9 @@ static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev)
static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev)
{
+ const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
+ const struct rtw89_ccx_regs *ccx = phy->ccx;
struct rtw89_ccx_para_info para = {0};
env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
@@ -3395,12 +3401,11 @@ static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev)
if (rtw89_phy_ifs_clm_th_update_check(rtwdev, ¶))
rtw89_phy_ifs_clm_set_th_reg(rtwdev);
- rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COLLECT_EN,
- true);
- rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_EN_MSK, true);
- rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_EN_MSK, true);
- rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_EN_MSK, true);
- rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_EN_MSK, true);
+ rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_collect_en_mask, true);
+ rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_en_mask, true);
+ rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_en_mask, true);
+ rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_en_mask, true);
+ rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_en_mask, true);
}
static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev,
@@ -3437,12 +3442,14 @@ static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev,
static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev)
{
+ const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
+ const struct rtw89_ccx_regs *ccx = phy->ccx;
- rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 0);
- rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 0);
- rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 1);
- rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1);
+ rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 0);
+ rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 0);
+ rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 1);
+ rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1);
env->ccx_ongoing = true;
}
@@ -3514,63 +3521,79 @@ static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev)
static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev)
{
+ const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
+ const struct rtw89_ccx_regs *ccx = phy->ccx;
u8 i = 0;
- if (rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_DONE_MSK) == 0) {
+ if (rtw89_phy_read32_mask(rtwdev, ccx->ifs_total_addr,
+ ccx->ifs_cnt_done_mask) == 0) {
rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
"Get IFS_CLM report Fail\n");
return false;
}
env->ifs_clm_tx =
- rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT,
- B_IFS_CLM_TX_CNT_MSK);
+ rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_tx_cnt_addr,
+ ccx->ifs_clm_tx_cnt_msk);
env->ifs_clm_edcca_excl_cca =
- rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT,
- B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK);
+ rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_tx_cnt_addr,
+ ccx->ifs_clm_edcca_excl_cca_fa_mask);
env->ifs_clm_cckcca_excl_fa =
- rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA,
- B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK);
+ rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_cca_addr,
+ ccx->ifs_clm_cckcca_excl_fa_mask);
env->ifs_clm_ofdmcca_excl_fa =
- rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA,
- B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK);
+ rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_cca_addr,
+ ccx->ifs_clm_ofdmcca_excl_fa_mask);
env->ifs_clm_cckfa =
- rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA,
- B_IFS_CLM_CCK_FA_MSK);
+ rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_fa_addr,
+ ccx->ifs_clm_cck_fa_mask);
env->ifs_clm_ofdmfa =
- rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA,
- B_IFS_CLM_OFDM_FA_MSK);
+ rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_fa_addr,
+ ccx->ifs_clm_ofdm_fa_mask);
env->ifs_clm_his[0] =
- rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T1_HIS_MSK);
+ rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr,
+ ccx->ifs_t1_his_mask);
env->ifs_clm_his[1] =
- rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T2_HIS_MSK);
+ rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr,
+ ccx->ifs_t2_his_mask);
env->ifs_clm_his[2] =
- rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T3_HIS_MSK);
+ rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr,
+ ccx->ifs_t3_his_mask);
env->ifs_clm_his[3] =
- rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T4_HIS_MSK);
+ rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr,
+ ccx->ifs_t4_his_mask);
env->ifs_clm_avg[0] =
- rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T1_AVG_MSK);
+ rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_l_addr,
+ ccx->ifs_t1_avg_mask);
env->ifs_clm_avg[1] =
- rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T2_AVG_MSK);
+ rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_l_addr,
+ ccx->ifs_t2_avg_mask);
env->ifs_clm_avg[2] =
- rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T3_AVG_MSK);
+ rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_h_addr,
+ ccx->ifs_t3_avg_mask);
env->ifs_clm_avg[3] =
- rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T4_AVG_MSK);
+ rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_h_addr,
+ ccx->ifs_t4_avg_mask);
env->ifs_clm_cca[0] =
- rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T1_CCA_MSK);
+ rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_l_addr,
+ ccx->ifs_t1_cca_mask);
env->ifs_clm_cca[1] =
- rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T2_CCA_MSK);
+ rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_l_addr,
+ ccx->ifs_t2_cca_mask);
env->ifs_clm_cca[2] =
- rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T3_CCA_MSK);
+ rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_h_addr,
+ ccx->ifs_t3_cca_mask);
env->ifs_clm_cca[3] =
- rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T4_CCA_MSK);
+ rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_h_addr,
+ ccx->ifs_t4_cca_mask);
env->ifs_clm_total_ifs =
- rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_TOTAL_CNT_MSK);
+ rtw89_phy_read32_mask(rtwdev, ccx->ifs_total_addr,
+ ccx->ifs_total_mask);
rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n",
env->ifs_clm_total_ifs);
@@ -3598,7 +3621,9 @@ static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev)
static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev,
struct rtw89_ccx_para_info *para)
{
+ const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
+ const struct rtw89_ccx_regs *ccx = phy->ccx;
u32 period = 0;
u32 unit_idx = 0;
@@ -3614,10 +3639,11 @@ static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev,
if (para->mntr_time != env->ifs_clm_mntr_time) {
rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time,
&period, &unit_idx);
- rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER,
- B_IFS_CLM_PERIOD_MSK, period);
- rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER,
- B_IFS_CLM_COUNTER_UNIT_MSK, unit_idx);
+ rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr,
+ ccx->ifs_clm_period_mask, period);
+ rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr,
+ ccx->ifs_clm_cnt_unit_mask,
+ unit_idx);
rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
"Update IFS-CLM time ((%d)) -> ((%d))\n",
@@ -3735,16 +3761,19 @@ static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev,
bool enable,
enum rtw89_phy_idx phy_idx)
{
+ const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
+ const struct rtw89_physts_regs *physts = phy->physts;
+
if (enable) {
- rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM,
- B_STS_DIS_TRIG_BY_FAIL);
- rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM,
- B_STS_DIS_TRIG_BY_BRK);
+ rtw89_phy_write32_clr(rtwdev, physts->setting_addr,
+ physts->dis_trigger_fail_mask);
+ rtw89_phy_write32_clr(rtwdev, physts->setting_addr,
+ physts->dis_trigger_brk_mask);
} else {
- rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM,
- B_STS_DIS_TRIG_BY_FAIL);
- rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM,
- B_STS_DIS_TRIG_BY_BRK);
+ rtw89_phy_write32_set(rtwdev, physts->setting_addr,
+ physts->dis_trigger_fail_mask);
+ rtw89_phy_write32_set(rtwdev, physts->setting_addr,
+ physts->dis_trigger_brk_mask);
}
}
@@ -4172,10 +4201,10 @@ static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi,
"igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n",
final_rssi, cck_cca_th, under_region, pd_val);
- rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_EN_V1,
- B_BMODE_PDTH_LIMIT_EN_MSK_V1, enable);
- rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_V1,
- B_BMODE_PDTH_LOWER_BOUND_MSK_V1, pd_val);
+ rtw89_phy_write32_mask(rtwdev, dig_regs->bmode_pd_reg,
+ dig_regs->bmode_cca_rssi_limit_en, enable);
+ rtw89_phy_write32_mask(rtwdev, dig_regs->bmode_pd_lower_bound_reg,
+ dig_regs->bmode_rssi_nocca_low_th_mask, pd_val);
}
void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev)
@@ -4729,7 +4758,73 @@ void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, bool scan)
}
}
+static const struct rtw89_ccx_regs rtw89_ccx_regs_ax = {
+ .setting_addr = R_CCX,
+ .edcca_opt_mask = B_CCX_EDCCA_OPT_MSK,
+ .measurement_trig_mask = B_MEASUREMENT_TRIG_MSK,
+ .trig_opt_mask = B_CCX_TRIG_OPT_MSK,
+ .en_mask = B_CCX_EN_MSK,
+ .ifs_cnt_addr = R_IFS_COUNTER,
+ .ifs_clm_period_mask = B_IFS_CLM_PERIOD_MSK,
+ .ifs_clm_cnt_unit_mask = B_IFS_CLM_COUNTER_UNIT_MSK,
+ .ifs_clm_cnt_clear_mask = B_IFS_COUNTER_CLR_MSK,
+ .ifs_collect_en_mask = B_IFS_COLLECT_EN,
+ .ifs_t1_addr = R_IFS_T1,
+ .ifs_t1_th_h_mask = B_IFS_T1_TH_HIGH_MSK,
+ .ifs_t1_en_mask = B_IFS_T1_EN_MSK,
+ .ifs_t1_th_l_mask = B_IFS_T1_TH_LOW_MSK,
+ .ifs_t2_addr = R_IFS_T2,
+ .ifs_t2_th_h_mask = B_IFS_T2_TH_HIGH_MSK,
+ .ifs_t2_en_mask = B_IFS_T2_EN_MSK,
+ .ifs_t2_th_l_mask = B_IFS_T2_TH_LOW_MSK,
+ .ifs_t3_addr = R_IFS_T3,
+ .ifs_t3_th_h_mask = B_IFS_T3_TH_HIGH_MSK,
+ .ifs_t3_en_mask = B_IFS_T3_EN_MSK,
+ .ifs_t3_th_l_mask = B_IFS_T3_TH_LOW_MSK,
+ .ifs_t4_addr = R_IFS_T4,
+ .ifs_t4_th_h_mask = B_IFS_T4_TH_HIGH_MSK,
+ .ifs_t4_en_mask = B_IFS_T4_EN_MSK,
+ .ifs_t4_th_l_mask = B_IFS_T4_TH_LOW_MSK,
+ .ifs_clm_tx_cnt_addr = R_IFS_CLM_TX_CNT,
+ .ifs_clm_edcca_excl_cca_fa_mask = B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK,
+ .ifs_clm_tx_cnt_msk = B_IFS_CLM_TX_CNT_MSK,
+ .ifs_clm_cca_addr = R_IFS_CLM_CCA,
+ .ifs_clm_ofdmcca_excl_fa_mask = B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK,
+ .ifs_clm_cckcca_excl_fa_mask = B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK,
+ .ifs_clm_fa_addr = R_IFS_CLM_FA,
+ .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK,
+ .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK,
+ .ifs_his_addr = R_IFS_HIS,
+ .ifs_t4_his_mask = B_IFS_T4_HIS_MSK,
+ .ifs_t3_his_mask = B_IFS_T3_HIS_MSK,
+ .ifs_t2_his_mask = B_IFS_T2_HIS_MSK,
+ .ifs_t1_his_mask = B_IFS_T1_HIS_MSK,
+ .ifs_avg_l_addr = R_IFS_AVG_L,
+ .ifs_t2_avg_mask = B_IFS_T2_AVG_MSK,
+ .ifs_t1_avg_mask = B_IFS_T1_AVG_MSK,
+ .ifs_avg_h_addr = R_IFS_AVG_H,
+ .ifs_t4_avg_mask = B_IFS_T4_AVG_MSK,
+ .ifs_t3_avg_mask = B_IFS_T3_AVG_MSK,
+ .ifs_cca_l_addr = R_IFS_CCA_L,
+ .ifs_t2_cca_mask = B_IFS_T2_CCA_MSK,
+ .ifs_t1_cca_mask = B_IFS_T1_CCA_MSK,
+ .ifs_cca_h_addr = R_IFS_CCA_H,
+ .ifs_t4_cca_mask = B_IFS_T4_CCA_MSK,
+ .ifs_t3_cca_mask = B_IFS_T3_CCA_MSK,
+ .ifs_total_addr = R_IFSCNT,
+ .ifs_cnt_done_mask = B_IFSCNT_DONE_MSK,
+ .ifs_total_mask = B_IFSCNT_TOTAL_CNT_MSK,
+};
+
+static const struct rtw89_physts_regs rtw89_physts_regs_ax = {
+ .setting_addr = R_PLCP_HISTOGRAM,
+ .dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL,
+ .dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK,
+};
+
const struct rtw89_phy_gen_def rtw89_phy_gen_ax = {
.cr_base = 0x10000,
+ .ccx = &rtw89_ccx_regs_ax,
+ .physts = &rtw89_physts_regs_ax,
};
EXPORT_SYMBOL(rtw89_phy_gen_ax);
@@ -336,8 +336,74 @@ struct rtw89_nbi_reg_def {
struct rtw89_reg_def notch2_en;
};
+struct rtw89_ccx_regs {
+ u32 setting_addr;
+ u32 edcca_opt_mask;
+ u32 measurement_trig_mask;
+ u32 trig_opt_mask;
+ u32 en_mask;
+ u32 ifs_cnt_addr;
+ u32 ifs_clm_period_mask;
+ u32 ifs_clm_cnt_unit_mask;
+ u32 ifs_clm_cnt_clear_mask;
+ u32 ifs_collect_en_mask;
+ u32 ifs_t1_addr;
+ u32 ifs_t1_th_h_mask;
+ u32 ifs_t1_en_mask;
+ u32 ifs_t1_th_l_mask;
+ u32 ifs_t2_addr;
+ u32 ifs_t2_th_h_mask;
+ u32 ifs_t2_en_mask;
+ u32 ifs_t2_th_l_mask;
+ u32 ifs_t3_addr;
+ u32 ifs_t3_th_h_mask;
+ u32 ifs_t3_en_mask;
+ u32 ifs_t3_th_l_mask;
+ u32 ifs_t4_addr;
+ u32 ifs_t4_th_h_mask;
+ u32 ifs_t4_en_mask;
+ u32 ifs_t4_th_l_mask;
+ u32 ifs_clm_tx_cnt_addr;
+ u32 ifs_clm_edcca_excl_cca_fa_mask;
+ u32 ifs_clm_tx_cnt_msk;
+ u32 ifs_clm_cca_addr;
+ u32 ifs_clm_ofdmcca_excl_fa_mask;
+ u32 ifs_clm_cckcca_excl_fa_mask;
+ u32 ifs_clm_fa_addr;
+ u32 ifs_clm_ofdm_fa_mask;
+ u32 ifs_clm_cck_fa_mask;
+ u32 ifs_his_addr;
+ u32 ifs_t4_his_mask;
+ u32 ifs_t3_his_mask;
+ u32 ifs_t2_his_mask;
+ u32 ifs_t1_his_mask;
+ u32 ifs_avg_l_addr;
+ u32 ifs_t2_avg_mask;
+ u32 ifs_t1_avg_mask;
+ u32 ifs_avg_h_addr;
+ u32 ifs_t4_avg_mask;
+ u32 ifs_t3_avg_mask;
+ u32 ifs_cca_l_addr;
+ u32 ifs_t2_cca_mask;
+ u32 ifs_t1_cca_mask;
+ u32 ifs_cca_h_addr;
+ u32 ifs_t4_cca_mask;
+ u32 ifs_t3_cca_mask;
+ u32 ifs_total_addr;
+ u32 ifs_cnt_done_mask;
+ u32 ifs_total_mask;
+};
+
+struct rtw89_physts_regs {
+ u32 setting_addr;
+ u32 dis_trigger_fail_mask;
+ u32 dis_trigger_brk_mask;
+};
+
struct rtw89_phy_gen_def {
u32 cr_base;
+ const struct rtw89_ccx_regs *ccx;
+ const struct rtw89_physts_regs *physts;
};
extern const struct rtw89_phy_gen_def rtw89_phy_gen_ax;
@@ -3,8 +3,75 @@
*/
#include "phy.h"
+#include "reg.h"
+
+static const struct rtw89_ccx_regs rtw89_ccx_regs_be = {
+ .setting_addr = R_CCX,
+ .edcca_opt_mask = B_CCX_EDCCA_OPT_MSK_V1,
+ .measurement_trig_mask = B_MEASUREMENT_TRIG_MSK,
+ .trig_opt_mask = B_CCX_TRIG_OPT_MSK,
+ .en_mask = B_CCX_EN_MSK,
+ .ifs_cnt_addr = R_IFS_COUNTER,
+ .ifs_clm_period_mask = B_IFS_CLM_PERIOD_MSK,
+ .ifs_clm_cnt_unit_mask = B_IFS_CLM_COUNTER_UNIT_MSK,
+ .ifs_clm_cnt_clear_mask = B_IFS_COUNTER_CLR_MSK,
+ .ifs_collect_en_mask = B_IFS_COLLECT_EN,
+ .ifs_t1_addr = R_IFS_T1,
+ .ifs_t1_th_h_mask = B_IFS_T1_TH_HIGH_MSK,
+ .ifs_t1_en_mask = B_IFS_T1_EN_MSK,
+ .ifs_t1_th_l_mask = B_IFS_T1_TH_LOW_MSK,
+ .ifs_t2_addr = R_IFS_T2,
+ .ifs_t2_th_h_mask = B_IFS_T2_TH_HIGH_MSK,
+ .ifs_t2_en_mask = B_IFS_T2_EN_MSK,
+ .ifs_t2_th_l_mask = B_IFS_T2_TH_LOW_MSK,
+ .ifs_t3_addr = R_IFS_T3,
+ .ifs_t3_th_h_mask = B_IFS_T3_TH_HIGH_MSK,
+ .ifs_t3_en_mask = B_IFS_T3_EN_MSK,
+ .ifs_t3_th_l_mask = B_IFS_T3_TH_LOW_MSK,
+ .ifs_t4_addr = R_IFS_T4,
+ .ifs_t4_th_h_mask = B_IFS_T4_TH_HIGH_MSK,
+ .ifs_t4_en_mask = B_IFS_T4_EN_MSK,
+ .ifs_t4_th_l_mask = B_IFS_T4_TH_LOW_MSK,
+ .ifs_clm_tx_cnt_addr = R_IFS_CLM_TX_CNT_V1,
+ .ifs_clm_edcca_excl_cca_fa_mask = B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK,
+ .ifs_clm_tx_cnt_msk = B_IFS_CLM_TX_CNT_MSK,
+ .ifs_clm_cca_addr = R_IFS_CLM_CCA_V1,
+ .ifs_clm_ofdmcca_excl_fa_mask = B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK,
+ .ifs_clm_cckcca_excl_fa_mask = B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK,
+ .ifs_clm_fa_addr = R_IFS_CLM_FA_V1,
+ .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK,
+ .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK,
+ .ifs_his_addr = R_IFS_HIS_V1,
+ .ifs_t4_his_mask = B_IFS_T4_HIS_MSK,
+ .ifs_t3_his_mask = B_IFS_T3_HIS_MSK,
+ .ifs_t2_his_mask = B_IFS_T2_HIS_MSK,
+ .ifs_t1_his_mask = B_IFS_T1_HIS_MSK,
+ .ifs_avg_l_addr = R_IFS_AVG_L_V1,
+ .ifs_t2_avg_mask = B_IFS_T2_AVG_MSK,
+ .ifs_t1_avg_mask = B_IFS_T1_AVG_MSK,
+ .ifs_avg_h_addr = R_IFS_AVG_H_V1,
+ .ifs_t4_avg_mask = B_IFS_T4_AVG_MSK,
+ .ifs_t3_avg_mask = B_IFS_T3_AVG_MSK,
+ .ifs_cca_l_addr = R_IFS_CCA_L_V1,
+ .ifs_t2_cca_mask = B_IFS_T2_CCA_MSK,
+ .ifs_t1_cca_mask = B_IFS_T1_CCA_MSK,
+ .ifs_cca_h_addr = R_IFS_CCA_H_V1,
+ .ifs_t4_cca_mask = B_IFS_T4_CCA_MSK,
+ .ifs_t3_cca_mask = B_IFS_T3_CCA_MSK,
+ .ifs_total_addr = R_IFSCNT_V1,
+ .ifs_cnt_done_mask = B_IFSCNT_DONE_MSK,
+ .ifs_total_mask = B_IFSCNT_TOTAL_CNT_MSK,
+};
+
+static const struct rtw89_physts_regs rtw89_physts_regs_be = {
+ .setting_addr = R_PLCP_HISTOGRAM,
+ .dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL,
+ .dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK,
+};
const struct rtw89_phy_gen_def rtw89_phy_gen_be = {
.cr_base = 0x20000,
+ .ccx = &rtw89_ccx_regs_be,
+ .physts = &rtw89_physts_regs_be,
};
EXPORT_SYMBOL(rtw89_phy_gen_be);
@@ -3998,6 +3998,7 @@
#define B_DBCC_80P80_SEL_EVM_RPT_EN BIT(0)
#define R_CCX 0x0C00
#define B_CCX_EDCCA_OPT_MSK GENMASK(6, 4)
+#define B_CCX_EDCCA_OPT_MSK_V1 GENMASK(7, 4)
#define B_MEASUREMENT_TRIG_MSK BIT(2)
#define B_CCX_TRIG_OPT_MSK BIT(1)
#define B_CCX_EN_MSK BIT(0)
@@ -4089,32 +4090,41 @@
#define B_SWSI_R_DATA_DONE_V1 BIT(26)
#define R_TX_COUNTER 0x1A40
#define R_IFS_CLM_TX_CNT 0x1ACC
+#define R_IFS_CLM_TX_CNT_V1 0x0ECC
#define B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK GENMASK(31, 16)
#define B_IFS_CLM_TX_CNT_MSK GENMASK(15, 0)
#define R_IFS_CLM_CCA 0x1AD0
+#define R_IFS_CLM_CCA_V1 0x0ED0
#define B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK GENMASK(31, 16)
#define B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK GENMASK(15, 0)
#define R_IFS_CLM_FA 0x1AD4
+#define R_IFS_CLM_FA_V1 0x0ED4
#define B_IFS_CLM_OFDM_FA_MSK GENMASK(31, 16)
#define B_IFS_CLM_CCK_FA_MSK GENMASK(15, 0)
#define R_IFS_HIS 0x1AD8
+#define R_IFS_HIS_V1 0x0ED8
#define B_IFS_T4_HIS_MSK GENMASK(31, 24)
#define B_IFS_T3_HIS_MSK GENMASK(23, 16)
#define B_IFS_T2_HIS_MSK GENMASK(15, 8)
#define B_IFS_T1_HIS_MSK GENMASK(7, 0)
#define R_IFS_AVG_L 0x1ADC
+#define R_IFS_AVG_L_V1 0x0EDC
#define B_IFS_T2_AVG_MSK GENMASK(31, 16)
#define B_IFS_T1_AVG_MSK GENMASK(15, 0)
#define R_IFS_AVG_H 0x1AE0
+#define R_IFS_AVG_H_V1 0x0EE0
#define B_IFS_T4_AVG_MSK GENMASK(31, 16)
#define B_IFS_T3_AVG_MSK GENMASK(15, 0)
#define R_IFS_CCA_L 0x1AE4
+#define R_IFS_CCA_L_V1 0x0EE4
#define B_IFS_T2_CCA_MSK GENMASK(31, 16)
#define B_IFS_T1_CCA_MSK GENMASK(15, 0)
#define R_IFS_CCA_H 0x1AE8
+#define R_IFS_CCA_H_V1 0x0EE8
#define B_IFS_T4_CCA_MSK GENMASK(31, 16)
#define B_IFS_T3_CCA_MSK GENMASK(15, 0)
#define R_IFSCNT 0x1AEC
+#define R_IFSCNT_V1 0x0EEC
#define B_IFSCNT_DONE_MSK BIT(16)
#define B_IFSCNT_TOTAL_CNT_MSK GENMASK(15, 0)
#define R_TXAGC_TP 0x1C04
@@ -4385,6 +4395,7 @@
#define B_PKT_POP_EN BIT(8)
#define R_SEG0R_PD 0x481C
#define R_SEG0R_PD_V1 0x4860
+#define R_SEG0R_PD_V2 0x6A74
#define R_SEG0R_EDCCA_LVL 0x4840
#define R_SEG0R_EDCCA_LVL_V1 0x4884
#define B_SEG0R_PPDU_LVL_MSK GENMASK(31, 24)
@@ -4503,8 +4514,10 @@
#define R_DCFO_COMP_S0_V1 0x4A40
#define B_DCFO_COMP_S0_V1_MSK GENMASK(13, 0)
#define R_BMODE_PDTH_V1 0x4B64
+#define R_BMODE_PDTH_V2 0x6708
#define B_BMODE_PDTH_LOWER_BOUND_MSK_V1 GENMASK(31, 24)
#define R_BMODE_PDTH_EN_V1 0x4B74
+#define R_BMODE_PDTH_EN_V2 0x6718
#define B_BMODE_PDTH_LIMIT_EN_MSK_V1 BIT(30)
#define R_CFO_COMP_SEG1_L 0x5384
#define R_CFO_COMP_SEG1_H 0x5388
@@ -185,6 +185,10 @@ static const struct rtw89_dig_regs rtw8851b_dig_regs = {
.seg0_pd_reg = R_SEG0R_PD_V1,
.pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
.pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1,
+ .bmode_pd_reg = R_BMODE_PDTH_EN_V1,
+ .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1,
+ .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1,
+ .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1,
.p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK},
.p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK},
.p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1},
@@ -478,6 +478,10 @@ static const struct rtw89_dig_regs rtw8852a_dig_regs = {
.seg0_pd_reg = R_SEG0R_PD,
.pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
.pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK,
+ .bmode_pd_reg = R_BMODE_PDTH_EN_V1,
+ .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1,
+ .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1,
+ .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1,
.p0_lna_init = {R_PATH0_LNA_INIT, B_PATH0_LNA_INIT_IDX_MSK},
.p1_lna_init = {R_PATH1_LNA_INIT, B_PATH1_LNA_INIT_IDX_MSK},
.p0_tia_init = {R_PATH0_TIA_INIT, B_PATH0_TIA_INIT_IDX_MSK},
@@ -310,6 +310,10 @@ static const struct rtw89_dig_regs rtw8852b_dig_regs = {
.seg0_pd_reg = R_SEG0R_PD_V1,
.pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
.pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1,
+ .bmode_pd_reg = R_BMODE_PDTH_EN_V1,
+ .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1,
+ .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1,
+ .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1,
.p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK},
.p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK},
.p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1},
@@ -146,6 +146,10 @@ static const struct rtw89_dig_regs rtw8852c_dig_regs = {
.seg0_pd_reg = R_SEG0R_PD,
.pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
.pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK,
+ .bmode_pd_reg = R_BMODE_PDTH_EN_V1,
+ .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1,
+ .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1,
+ .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1,
.p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK},
.p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK},
.p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1},