From patchwork Sat Aug 31 02:13:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Li Zetao X-Patchwork-Id: 826302 Received: from szxga06-in.huawei.com (szxga06-in.huawei.com [45.249.212.32]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2490913AD09; Sat, 31 Aug 2024 02:05:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.32 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725069932; cv=none; b=twvmSDe6XODkGW6th0fdbRY8cJV7Y8qC06lRip0NVinzi2Lyhpzip7OJFAkVwYWm0ytbab0pyE+zCxC+LqCY9qxkmCgdcAFPYYjX/ngwgChTVEAZxlz16oPRfvr8t6YT8Bl75k6ZfQeCySmyLLnr5Z9CX2b5ARwJxFGP6QNa0+w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725069932; c=relaxed/simple; bh=PLWWPbjLHKrKTKHzeoxZ6f3CUM3xbK62BPaOLTVoTi4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WBPkq+7DeHxb0JLPTr/vot4Oq6cPjp8E3YsBHw1C2MHrvWrjTPIP+dA7c1DhBICgEC6iX8yCMyWFWEX9wiSFnLJpr2zjbG5kYO2hF0AVY9n0/BQSUtnZDr+OT2cfxZBKsHXYdH9d37pFsObCQ6HKJwfEEKyenQ24EboLU5jOEQ8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.32 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.234]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4WwdbP2Q9Nz1xwhw; Sat, 31 Aug 2024 10:03:29 +0800 (CST) Received: from kwepemd500012.china.huawei.com (unknown [7.221.188.25]) by mail.maildlp.com (Postfix) with ESMTPS id 254B6140109; Sat, 31 Aug 2024 10:05:28 +0800 (CST) Received: from huawei.com (10.90.53.73) by kwepemd500012.china.huawei.com (7.221.188.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.34; Sat, 31 Aug 2024 10:05:26 +0800 From: Li Zetao To: , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH net-next 10/12] net: xilinx: axienet: Convert using devm_clk_get_optional_enabled() in axienet_probe() Date: Sat, 31 Aug 2024 10:13:32 +0800 Message-ID: <20240831021334.1907921-11-lizetao1@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240831021334.1907921-1-lizetao1@huawei.com> References: <20240831021334.1907921-1-lizetao1@huawei.com> Precedence: bulk X-Mailing-List: linux-wireless@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To kwepemd500012.china.huawei.com (7.221.188.25) Use devm_clk_get_optional_enabled() instead of devm_clk_get_optional() + clk_prepare_enable(), which can make the clk consistent with the device life cycle and reduce the risk of unreleased clk resources. Since the device framework has automatically released the clk resource, there is no need to execute clk_disable_unprepare(clk) on the error path. Signed-off-by: Li Zetao --- drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c index fe6a0e2e463f..48b41e95aa74 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c @@ -2584,22 +2584,17 @@ static int axienet_probe(struct platform_device *pdev) seqcount_mutex_init(&lp->hw_stats_seqcount, &lp->stats_lock); INIT_DEFERRABLE_WORK(&lp->stats_work, axienet_refresh_stats); - lp->axi_clk = devm_clk_get_optional(&pdev->dev, "s_axi_lite_clk"); - if (!lp->axi_clk) { + lp->axi_clk = devm_clk_get_optional_enabled(&pdev->dev, "s_axi_lite_clk"); + if (!lp->axi_clk) /* For backward compatibility, if named AXI clock is not present, * treat the first clock specified as the AXI clock. */ - lp->axi_clk = devm_clk_get_optional(&pdev->dev, NULL); - } + lp->axi_clk = devm_clk_get_optional_enabled(&pdev->dev, NULL); + if (IS_ERR(lp->axi_clk)) { ret = PTR_ERR(lp->axi_clk); goto free_netdev; } - ret = clk_prepare_enable(lp->axi_clk); - if (ret) { - dev_err(&pdev->dev, "Unable to enable AXI clock: %d\n", ret); - goto free_netdev; - } lp->misc_clks[0].id = "axis_clk"; lp->misc_clks[1].id = "ref_clk"; @@ -2915,7 +2910,6 @@ static int axienet_probe(struct platform_device *pdev) axienet_mdio_teardown(lp); cleanup_clk: clk_bulk_disable_unprepare(XAE_NUM_MISC_CLOCKS, lp->misc_clks); - clk_disable_unprepare(lp->axi_clk); free_netdev: free_netdev(ndev); @@ -2939,7 +2933,6 @@ static void axienet_remove(struct platform_device *pdev) axienet_mdio_teardown(lp); clk_bulk_disable_unprepare(XAE_NUM_MISC_CLOCKS, lp->misc_clks); - clk_disable_unprepare(lp->axi_clk); free_netdev(ndev); }