@@ -276,10 +276,16 @@ struct qcom_pcie {
struct dentry *debugfs;
bool suspended;
bool use_pm_opp;
+ int aspm_state; /* Store ASPM state used in pre & post scale bus bw */
};
#define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
+static void qcom_pcie_host_post_scale_bus_bw(struct pci_host_bridge *bridge,
+ struct pci_dev *pdev, int current_speed);
+static int qcom_pcie_host_pre_scale_bus_bw(struct pci_host_bridge *bridge,
+ struct pci_dev *pdev, int current_speed);
+
static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
{
gpiod_set_value_cansleep(pcie->reset, 1);
@@ -1263,6 +1269,8 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp)
goto err_assert_reset;
}
+ pp->bridge->pre_scale_bus_bw = qcom_pcie_host_pre_scale_bus_bw;
+ pp->bridge->post_scale_bus_bw = qcom_pcie_host_post_scale_bus_bw;
return 0;
err_assert_reset:
@@ -1328,6 +1336,61 @@ static int qcom_pcie_set_icc_opp(struct qcom_pcie *pcie, int speed, int width)
return ret;
}
+static int qcom_pcie_scale_bw(struct dw_pcie_rp *pp, int speed)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct qcom_pcie *pcie = to_qcom_pcie(pci);
+ u32 offset, status, width;
+
+ offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+ status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
+
+ width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status);
+
+ return qcom_pcie_set_icc_opp(pcie, speed, width);
+}
+
+static void qcom_pcie_host_post_scale_bus_bw(struct pci_host_bridge *bridge,
+ struct pci_dev *pdev, int current_speed)
+{
+ struct dw_pcie_rp *pp = bridge->bus->sysdata;
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct qcom_pcie *pcie = to_qcom_pcie(pci);
+ struct pci_dev *child;
+
+ /* Get function 0 of downstream device */
+ list_for_each_entry(child, &pdev->subordinate->devices, bus_list)
+ if (PCI_FUNC(child->devfn) == 0)
+ break;
+
+ pci_enable_link_state_locked(child, pcie->aspm_state);
+
+ qcom_pcie_scale_bw(pp, current_speed);
+}
+
+static int qcom_pcie_host_pre_scale_bus_bw(struct pci_host_bridge *bridge,
+ struct pci_dev *pdev, int target_speed)
+{
+ struct dw_pcie_rp *pp = bridge->bus->sysdata;
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct qcom_pcie *pcie = to_qcom_pcie(pci);
+ struct pci_dev *child;
+
+ /* Get function 0 of downstream device */
+ list_for_each_entry(child, &pdev->subordinate->devices, bus_list)
+ if (PCI_FUNC(child->devfn) == 0)
+ break;
+ /*
+ * QCOM controllers doesn't support link re-train with ASPM enabled.
+ * Disable ASPM as part of pre_bus_bw() and enable them back as
+ * part of post_bus_bw().
+ */
+ pcie->aspm_state = pcie_aspm_enabled(child);
+ pci_disable_link_state_locked(child, PCIE_LINK_STATE_ALL);
+
+ return qcom_pcie_scale_bw(pp, target_speed);
+}
+
static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {
.init = qcom_pcie_host_init,
.deinit = qcom_pcie_host_deinit,
QCOM PCIe controllers need to disable ASPM before initiating link re-train. So as part of pre_bw_scale() disable ASPM and as part of post_scale_bus_bw() enable ASPM back. As the driver needs to enable the ASPM states that are enabled by the system, save PCI ASPM states before disabling them and in post_scale_bus_bw() use the saved ASPM states to enable back the ASPM. Update ICC & OPP votes based on the requested speed so that RPMh votes get updated based on the speed. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> --- drivers/pci/controller/dwc/pcie-qcom.c | 63 ++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+)