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Mon, 2 Jan 2023 14:46:51 +0000 From: Aditya Garg To: Hector Martin , "aspriel@gmail.com" , "hante.meuleman@broadcom.com" , "kvalo@kernel.org" , "davem@davemloft.net" , "edumazet@google.com" , "kuba@kernel.org" , "pabeni@redhat.com" , "lina@asahilina.net" , "franky.lin@broadcom.com" , Arend van Spriel CC: Orlando Chamberlain , "brcm80211-dev-list@broadcom.com" , "brcm80211-dev-list.pdl@broadcom.com" , "linux-wireless@vger.kernel.org" , LKML , Asahi Linux Subject: [PATCH v2 1/2] brcmfmac: Use separate struct to declare firmware names for Apple OTP chips Thread-Topic: [PATCH v2 1/2] brcmfmac: Use separate struct to declare firmware names for Apple OTP chips Thread-Index: AQHZHrkMuK4g+OysPUWm6aVQADl1dg== Date: Mon, 2 Jan 2023 14:46:51 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-tmn: [lE+doef27XN+R3eLz67aI62vxHZFpk3vwOnVbrHr9y1HW2VNOe0cXUIxLoCQmNwl] x-ms-publictraffictype: Email x-ms-traffictypediagnostic: BM1PR01MB0931:EE_|PN2PR01MB9277:EE_ x-ms-office365-filtering-correlation-id: fb39b637-d25a-428a-01ed-08daecd02f0f x-microsoft-antispam: BCL:0; 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It uses the BRCM4355 chip which is also found in Apple hardware. However this commit causes conflicts in the firmware naming between Apple hardware, which supports OTP and other non-Apple hardwares. So, this patch makes these Apple chips use their own firmware table so as to avoid possible conflicts like these in the future. Signed-off-by: Aditya Garg --- .../broadcom/brcm80211/brcmfmac/pcie.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c index ae57a9a3a..ad7a780cd 100644 --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c @@ -92,10 +92,13 @@ static const struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = { BRCMF_FW_ENTRY(BRCM_CC_43664_CHIP_ID, 0xFFFFFFF0, 4366C), BRCMF_FW_ENTRY(BRCM_CC_43666_CHIP_ID, 0xFFFFFFF0, 4366C), BRCMF_FW_ENTRY(BRCM_CC_4371_CHIP_ID, 0xFFFFFFFF, 4371), - BRCMF_FW_ENTRY(BRCM_CC_4378_CHIP_ID, 0xFFFFFFFF, 4378B1), /* revision ID 3 */ BRCMF_FW_ENTRY(CY_CC_89459_CHIP_ID, 0xFFFFFFFF, 4355), }; +static const struct brcmf_firmware_mapping brcmf_pcie_otp_fwnames[] = { + BRCMF_FW_ENTRY(BRCM_CC_4378_CHIP_ID, 0xFFFFFFFF, 4378B1), /* revision ID 3 */ +}; + #define BRCMF_PCIE_FW_UP_TIMEOUT 5000 /* msec */ #define BRCMF_PCIE_REG_MAP_SIZE (32 * 1024) @@ -2165,10 +2168,16 @@ brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo) { ".clm_blob", devinfo->clm_name }, }; - fwreq = brcmf_fw_alloc_request(devinfo->ci->chip, devinfo->ci->chiprev, - brcmf_pcie_fwnames, - ARRAY_SIZE(brcmf_pcie_fwnames), - fwnames, ARRAY_SIZE(fwnames)); + if (devinfo->otp.valid) + fwreq = brcmf_fw_alloc_request(devinfo->ci->chip, devinfo->ci->chiprev, + brcmf_pcie_otp_fwnames, + ARRAY_SIZE(brcmf_pcie_otp_fwnames), + fwnames, ARRAY_SIZE(fwnames)); + else + fwreq = brcmf_fw_alloc_request(devinfo->ci->chip, devinfo->ci->chiprev, + brcmf_pcie_fwnames, + ARRAY_SIZE(brcmf_pcie_fwnames), + fwnames, ARRAY_SIZE(fwnames)); if (!fwreq) return NULL;