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[209.132.180.67]) by mx.google.com with ESMTP id f12si2049942pfk.9.2017.02.28.07.16.15; Tue, 28 Feb 2017 07:16:15 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752713AbdB1PP6 (ORCPT + 25 others); Tue, 28 Feb 2017 10:15:58 -0500 Received: from mail-pg0-f41.google.com ([74.125.83.41]:36326 "EHLO mail-pg0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752430AbdB1PPv (ORCPT ); Tue, 28 Feb 2017 10:15:51 -0500 Received: by mail-pg0-f41.google.com with SMTP id s67so6270233pgb.3 for ; Tue, 28 Feb 2017 07:15:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id; bh=oR/RlCDmI+ROhg6Tzcmg4aivVxlyVsk2M0mXo4mKFMs=; b=CiLuTIN7Ay2VcHT3ycSFhPfEsauORPXN3mD18ObPyn83Tv0JYBJLL5SJOLMMMX/dyx wVF8QR0/TJKUvVilw2weVLeAkeF/hdSos6ObkTPsEtSAPau/7D5fSP9lFX+f/nMyRqj0 RDWSLYG3+KvQ5wJ8XTrI2rp0d36cjKjp+144c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id; bh=oR/RlCDmI+ROhg6Tzcmg4aivVxlyVsk2M0mXo4mKFMs=; b=ALr9nv6gbJ4U+MbjPTSVzaleNxnEf2Icbhqg5QkdINQCFCFeRH+D5ll/KH8ojOzBSF eayYlhKdOFGjvu3SXgVXWDkHEKIZGSxiYS34+GVcvyKmA7KzTwk5VRfYpQ4cxIqkGH0T YyBMMGPFKrRhnNFdHY5w+CnXFcDpisXRRY4OMkNBADcjGUJ5lmWFNHnd7mqxqXHi69AS hDE5jTeMCVwe0v4o6qOfw2139BVBbSTyHPTTLGEhewMtRK/tuc1VxlprUws9tA8JEtY7 6lW2ScBOdqjPrwbREZfEk7rb4T3FMqk+tIbUwAxyH5jsy43V9kVeQHoC2fMaEC0LvgOw NvMQ== X-Gm-Message-State: AMke39lzWMKucl6bbVVm3kYiyKimTgUKgtdl4Au9RtTpEnxVhl6ojNJ/gWMRRYil/b0nBDAo X-Received: by 10.84.173.228 with SMTP id p91mr3612499plb.121.1488294478816; Tue, 28 Feb 2017 07:07:58 -0800 (PST) Received: from localhost.localdomain ([103.192.224.50]) by smtp.gmail.com with ESMTPSA id c64sm4926145pfa.45.2017.02.28.07.07.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 28 Feb 2017 07:07:57 -0800 (PST) From: Leo Yan To: Rob Herring , Mark Rutland , Mathieu Poirier , Leo Yan , Greg Kroah-Hartman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org Subject: [PATCH v2 0/3] coresight: enable debug module Date: Tue, 28 Feb 2017 23:06:57 +0800 Message-Id: <1488294420-14188-1-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ARMv8 architecture reference manual (ARM DDI 0487A.k) Chapter H7 "The Sample-based Profiling Extension" has description for sampling registers, we can utilize these registers to check program counter value with combined CPU exception level, secure state, etc. So this is helpful for CPU lockup bugs, e.g. if one CPU has run into infinite loop with IRQ disabled; the 'hang' CPU cannot switch context and handle any interrupt, so it cannot handle SMP call for stack dump, etc. This patch series is to enable coresight debug module with sample-based registers and register call back notifier for PCSR register dumping when panic happens, so we can see below dumping info for panic; and this patch series has considered the conditions for access permission for debug registers self, so this can avoid access debug registers when CPU power domain is off; the driver also try to figure out the CPU is in secure or non-secure state. ARM external debug module: CPU[0]: EDPRSR: 0000000b (Power:On DLK:Unlock) EDPCSR: [] handle_IPI+0xe4/0x150 EDCIDSR: 00000000 EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0) CPU[1]: EDPRSR: 0000000b (Power:On DLK:Unlock) EDPCSR: [] debug_notifier_call+0x108/0x288 EDCIDSR: 00000000 EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0) [...] This patch series has been verified on 96boards Hikey. Changes from v1: * According to Mike Leach suggestion, remove the binding for debug module clocks which have been directly provided by CPU clocks. * According to Mathieu Poirier suggestion, add function of_coresight_get_cpu() and some minor refactors for debug module driver. Changes from RFC: * According to Mike Leach suggestion, added check for EDPRSR to avoid lockup; added supporting EDVIDSR and EDCIDSR registers; * According to Mark Rutland and Mathieu Poirier suggestion, rewrote the documentation for DT binding; * According to Mark and Mathieu suggestion, refined debug driver; Leo Yan (3): coresight: bindings for debug module coresight: refactor with function of_coresight_get_cpu coresight: add support for debug module .../devicetree/bindings/arm/coresight-debug.txt | 40 +++ drivers/hwtracing/coresight/Kconfig | 10 + drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-debug.c | 378 +++++++++++++++++++++ drivers/hwtracing/coresight/of_coresight.c | 35 +- include/linux/coresight.h | 2 + 6 files changed, 454 insertions(+), 12 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/coresight-debug.txt create mode 100644 drivers/hwtracing/coresight/coresight-debug.c -- 2.7.4 Reviewed-by: Mathieu Poirier Acked-by: Rob Herring