From patchwork Tue May 23 14:23:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriele Paoloni X-Patchwork-Id: 100378 Delivered-To: patch@linaro.org Received: by 10.182.142.97 with SMTP id rv1csp1898366obb; Tue, 23 May 2017 07:25:05 -0700 (PDT) X-Received: by 10.98.44.140 with SMTP id s134mr32644669pfs.193.1495549505693; Tue, 23 May 2017 07:25:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495549505; cv=none; d=google.com; s=arc-20160816; b=IU/ekgcZ0Hf43Ve9BehPWhsNmwUQ8IhT22H6sSYFvI7pAYqPYMP8SdKtxV98/M2Brz bSLTmP2TkMo/ThPEcx3yBcIgEk/quK0zqI14xed+A7+5EiCN9a2AltRHP+n8iidj3vKg pl2cIVe/QuPz5MY8c/XbpaGM+wSFyJB5Qu/v5N4jiOa+yr//Y3bpt8LtVIAyC6dQMxqq 2s+m1UITy5/+IAL06uocW3UDEvPkIEB9Faieoe9Xjln7ZQiNZ89+q67U2kHXSejEkWF3 jinsDqXyKG6cTyQ+q06e7qrj5Jt/jFnxe6qfk717hRZakxXdHVoKsEx+ks0f0q6HW36R OXUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=Z1cTojVBX1UG5BLREbzyQlo3vbD2nWTFF7vctKMH4ZU=; b=hjKRXNRU/sXj4124lB28A6FCPCtlwhN/Bij53IR+XBHAtb64kQaU3fXIvoycCV0wIp m1Ucnas0bdCw0b/oepP2/qtLpGjjS5BDQ4KnYwxv8uqEGGYkd2jTD4QIg161N8f6iPaw AdrUfmPWJVpLrVZIeWPNaRyjeQI8SSs3sXfZ0FCQZUTa3Jw9nWLq/SCyTFI/s3UPy5XE YKDPqF4XywAGmb1cwmoMSFRq2FGbgHnzpfREnUxrJBTE1ixiUZdPakf10mVwjOw+vPmG 0n/MXxGYZknpbkecy9k2VgLphnAvZqBbIflqM92v5DiZjun+m/VYUGd74Lehzd6O0loo ljpg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 7si20707328pll.337.2017.05.23.07.25.05; Tue, 23 May 2017 07:25:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030514AbdEWOYr (ORCPT + 25 others); Tue, 23 May 2017 10:24:47 -0400 Received: from szxga03-in.huawei.com ([45.249.212.189]:6884 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1762343AbdEWOYi (ORCPT ); Tue, 23 May 2017 10:24:38 -0400 Received: from 172.30.72.55 (EHLO dggeml405-hub.china.huawei.com) ([172.30.72.55]) by dggrg03-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOE00892; Tue, 23 May 2017 22:24:20 +0800 (CST) Received: from G00308965-DELL1.china.huawei.com (10.203.181.156) by dggeml405-hub.china.huawei.com (10.3.17.49) with Microsoft SMTP Server id 14.3.301.0; Tue, 23 May 2017 22:24:12 +0800 From: Gabriele Paoloni To: , CC: , , , , , , , Subject: [PATCH v5 0/2] add MSI support for PCIe port services and DPC IRQ support Date: Tue, 23 May 2017 15:23:57 +0100 Message-ID: <1495549439-10372-1-git-send-email-gabriele.paoloni@huawei.com> X-Mailer: git-send-email 2.7.1.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.203.181.156] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.59244616.0270, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: adbc7e3337af5738822c4f5cc80b0b10 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: gabriele paoloni This patchset: 1) adds support for MSI interrupt vectors to be used for Roor Port services 2) adds support for DPC Root Port service interrupt The patchset has been tested on Hisilicon Hip08 Chipset Changes from v4: - removed meaningless comment Changes from v3: - removed 2 extra lines at the bottom of comments Changes from v2: - Fixed comment mismatch for function pcie_port_enable_irq_vec - removed redundant commet on pci_irq_vector() Changes from v1: According to comments from Christoph Hellwig in https://www.spinics.net/lists/kernel/msg2508842.html and https://www.spinics.net/lists/kernel/msg2508850.html - reduced the calls of pci_alloc_irq_vectors by ORing PCI_IRQ_MSIX and PCI_IRQ_MSI - used a unique macro for the max number of MSI/MSIx interrupt vectors - reworked pcie_init_service_irqs() to call pci_alloc_irq_vectors() only for legacy IRQ Gabriele Paoloni (1): PCI/portdrv: add support for different MSI interrupts for PCIe port services gabriele paoloni (1): PCI/portdrv: allocate MSI/MSIx vector for DPC RP service drivers/pci/pcie/portdrv.h | 8 ++++-- drivers/pci/pcie/portdrv_core.c | 63 +++++++++++++++++++++++++++++------------ 2 files changed, 50 insertions(+), 21 deletions(-) -- 2.7.4