From patchwork Mon Jan 8 17:32:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 123755 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp3003035qgn; Mon, 8 Jan 2018 09:34:29 -0800 (PST) X-Google-Smtp-Source: ACJfBota4coZTth1sTKnX9SZG78PyhiUSt/nf7cSwo/HV4LStto+0G1Uw97pRV29yjFp0CDtD/8A X-Received: by 10.99.180.76 with SMTP id n12mr887605pgu.8.1515432869481; Mon, 08 Jan 2018 09:34:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515432869; cv=none; d=google.com; s=arc-20160816; b=AQV0mx4GcCudG87K0XOI41jZILnExg8R8aP5ltk0Aj60a+dl2RLBdEPZfMFlTQOlH2 1qr6lhDdGbP4jjuYI7J7OTHYph9+ghsi6azExMmCiB71+9f0E/b4zu+MAa06bSJjafBU 4oWVeP6ld6iFv3tciHD5rPkgo7nOeDeFr58drr8N9l3QiVEvh8P2lEVKtclmFkQIMkXv XcmZl/alm2raTgMeCwX9uW+AEgWbYAvQPEWjWVixZFQIYv7MZE5OMqf7cF/h3oV8ZkiL cvrkB7WfY6Tqzn6anRef88qzipVBU2SjTgp/ZbHpCFsVj/vttRqWUTko9XG5jngv97c3 3KrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :arc-authentication-results; bh=4UkTP1t7Maoat9wxDYMxa2oD8pZtiMMyuMOHS5b5uRg=; b=c4xYceTtGiShVQQCWlwCJHGXj8Ezg+C+crO5reXb88X4e0eLJdN3RQh2mpggON/jJN Kx+vNr1KUM3lIsu7Ejen/3Eoc07xMeE13sC8YguPjphKsLJm5vAKRbl8vhJ2x2SBCnNR 4FlTNWB0dp9ormVzCQZjqpP/H7LoqyUNYseCj9FXfQckrysj9bzAZnhK2vfH4T+LqF3q KpOYTpauQ+9db/pjjbkuzxPpw5nq/Ra8lrchrMmeGATMj7IV2SXUJ06ERYyg6VNAON5H LgZgMGizg8GBVPHEMp8i/1opfxnGdD+i1eWMhnLegn3TUe1oRUNZVhn+1i0YC9+jPpUw vHJQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z8si3116pgp.323.2018.01.08.09.34.29; Mon, 08 Jan 2018 09:34:29 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754330AbeAHRcl (ORCPT + 28 others); Mon, 8 Jan 2018 12:32:41 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:42826 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754288AbeAHRcj (ORCPT ); Mon, 8 Jan 2018 12:32:39 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2EBE780D; Mon, 8 Jan 2018 09:32:39 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id F3DF03F487; Mon, 8 Jan 2018 09:32:38 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id E83BB1AE17F0; Mon, 8 Jan 2018 17:32:40 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, lorenzo.pieralisi@arm.com, christoffer.dall@linaro.org, linux-kernel@vger.kernel.org, shankerd@codeaurora.org, jnair@caviumnetworks.com, Will Deacon Subject: [PATCH v3 00/13] arm64 kpti hardening and variant 2 workarounds Date: Mon, 8 Jan 2018 17:32:25 +0000 Message-Id: <1515432758-26440-1-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi all, This is version three of the patches previously posted here: v1: http://lists.infradead.org/pipermail/linux-arm-kernel/2018-January/551838.html v2: http://lists.infradead.org/pipermail/linux-arm-kernel/2018-January/552085.html Changes since v2: * Fix typo in comment * Include Falkor hardening from Shanker * Add ThunderX2 MIDRs (subsequent patches under review) * Avoid applying hardening from preemtible context * Fix stack offsets in hyp SMC call Cheers, Will --->8 Jayachandran C (1): arm64: cputype: Add MIDR values for Cavium ThunderX2 CPUs Marc Zyngier (3): arm64: Move post_ttbr_update_workaround to C code arm64: KVM: Use per-CPU vector when BP hardening is enabled arm64: KVM: Make PSCI_VERSION a fast path Shanker Donthineni (1): arm64: Implement branch predictor hardening for Falkor Will Deacon (8): arm64: use RET instruction for exiting the trampoline arm64: Kconfig: Reword UNMAP_KERNEL_AT_EL0 kconfig entry arm64: Take into account ID_AA64PFR0_EL1.CSV3 arm64: cpufeature: Pass capability structure to ->enable callback drivers/firmware: Expose psci_get_version through psci_ops structure arm64: Add skeleton to harden the branch predictor against aliasing attacks arm64: cputype: Add missing MIDR values for Cortex-A72 and Cortex-A75 arm64: Implement branch predictor hardening for affected Cortex-A CPUs arch/arm/include/asm/kvm_mmu.h | 10 +++ arch/arm64/Kconfig | 30 +++++-- arch/arm64/include/asm/assembler.h | 13 --- arch/arm64/include/asm/cpucaps.h | 4 +- arch/arm64/include/asm/cputype.h | 7 ++ arch/arm64/include/asm/kvm_asm.h | 2 + arch/arm64/include/asm/kvm_mmu.h | 38 +++++++++ arch/arm64/include/asm/mmu.h | 37 +++++++++ arch/arm64/include/asm/sysreg.h | 2 + arch/arm64/kernel/Makefile | 4 + arch/arm64/kernel/bpi.S | 87 ++++++++++++++++++++ arch/arm64/kernel/cpu_errata.c | 161 +++++++++++++++++++++++++++++++++++++ arch/arm64/kernel/cpufeature.c | 13 ++- arch/arm64/kernel/entry.S | 19 ++++- arch/arm64/kvm/hyp/entry.S | 12 +++ arch/arm64/kvm/hyp/switch.c | 25 +++++- arch/arm64/mm/context.c | 11 +++ arch/arm64/mm/fault.c | 17 ++++ arch/arm64/mm/proc.S | 3 +- drivers/firmware/psci.c | 2 + include/linux/psci.h | 1 + virt/kvm/arm/arm.c | 8 +- 22 files changed, 474 insertions(+), 32 deletions(-) create mode 100644 arch/arm64/kernel/bpi.S -- 2.1.4