From patchwork Fri Jun 28 14:35:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 168094 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp3782461ilk; Fri, 28 Jun 2019 07:37:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqzoHb57Ys3Oevjsr5hj4j0PhlYXVB+V67KI41Hg+LemtH0ecinRbuDzyZuXcMDpOyVIgWUk X-Received: by 2002:a63:e018:: with SMTP id e24mr9509230pgh.361.1561732662154; Fri, 28 Jun 2019 07:37:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561732662; cv=none; d=google.com; s=arc-20160816; b=n0NjwX+CfE72KRB1tYMv84mNS5XHr2x5FHfkuSzX6Z5/1SCwG3a8Ku19mwNvBFpFum s7dAU8qHLzo1xJxwNs2n5+ZX/yGduwXLsxrlH1eMBV6it3lvsoiXDm3M1w1K+4ME7pvU jQeMedC7WK5QENxF/NfAUtHqve1qlnkucFTJQj/ay7nzZ+hQ92+E3I8oazB5f/5w8/aq m30N9+ME/2aJJY/J9b2W84FFCJd3c8FWMpPTE+9twsXFLVTa9OQpLav1F2btLq1NwFPX 5/079NrnI1cU2hTEWHThpVWIWxw0TcK3GMbynIA92VrX7BS32zXbmOb3risZ7hfVq/Kr wdqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from; bh=iC18Jt6LrPvU3kUdzCEWhtpgaYXUAgKvPtCf9GNecrU=; b=isOH3d3ezK921gpW9CLh8qFfBz88EVMXYcbj1zpcYkhb7BQ4b2EbuR0xBeV9j8nVnF GGn6hbD6u6D1gJOFan4cH/NE6n4ok2p54bx4Mj+VCtX4q29FmdcR7zWKPPuXOSWaAxYW fOnNcKMICzqaP+Z1ceuo0dfpvw+FDSpLTGUJFzn/dSdAuabpzWmR+Rr27jkLj57K79uc 9hfRdTp/f39mWy6Q/6T7zZTXY8t2CPuT7jGUpYKqZhMqxZb2xk59YwRSehbiT0UbcG7v VCunjYE+Hof5UmCu1yvjm0Q0I7l6NP/UC4xCnGUE6smos5blsMz0PDNVNAt5AFLVIXQp +zTw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b21si2276650plz.21.2019.06.28.07.37.41; Fri, 28 Jun 2019 07:37:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726860AbfF1Oha (ORCPT + 30 others); Fri, 28 Jun 2019 10:37:30 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:57372 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726785AbfF1Oh3 (ORCPT ); Fri, 28 Jun 2019 10:37:29 -0400 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 67663DD812BA72D3E07C; Fri, 28 Jun 2019 22:37:27 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.439.0; Fri, 28 Jun 2019 22:37:20 +0800 From: John Garry To: , , , , , , , , , , , , CC: , , , , , John Garry Subject: [PATCH v3 0/4] Perf uncore PMU event alias support for Hisi hip08 ARM64 platform Date: Fri, 28 Jun 2019 22:35:48 +0800 Message-ID: <1561732552-143038-1-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 2.8.1 MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patchset adds support for uncore PMU event aliasing for HiSilicon hip08 ARM64 platform. We can now get proper event description for uncore events for the perf tool. For HHA, DDRC, and L3C JSONs, we don't have all the event info yet, so I will seek it out to update the JSONs later. Changes to v3: - Omit "perf pmu: Fix uncore PMU alias list for ARM64", as it has already been picked up - Add comment for pmu_uncore_alias_match() Changes to v2: - Use strtok_r() in pmu_uncore_alias_match() - from "sccl" from uncore aliases John Garry (4): perf pmu: Support more complex PMU event aliasing perf jevents: Add support for Hisi hip08 DDRC PMU aliasing perf jevents: Add support for Hisi hip08 HHA PMU aliasing perf jevents: Add support for Hisi hip08 L3C PMU aliasing .../arm64/hisilicon/hip08/uncore-ddrc.json | 44 ++++++++++++++++ .../arm64/hisilicon/hip08/uncore-hha.json | 51 +++++++++++++++++++ .../arm64/hisilicon/hip08/uncore-l3c.json | 37 ++++++++++++++ tools/perf/pmu-events/jevents.c | 3 ++ tools/perf/util/pmu.c | 46 +++++++++++++++-- 5 files changed, 176 insertions(+), 5 deletions(-) create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-ddrc.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-hha.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08/uncore-l3c.json -- 2.17.1 Acked-by: Jiri Olsa