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[209.132.180.67]) by mx.google.com with ESMTP id l7si4493238pgq.631.2017.11.27.23.19.31; Mon, 27 Nov 2017 23:19:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=PwkLMFyw; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751838AbdK1HT3 (ORCPT + 28 others); Tue, 28 Nov 2017 02:19:29 -0500 Received: from mail-pl0-f67.google.com ([209.85.160.67]:43697 "EHLO mail-pl0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750907AbdK1HT2 (ORCPT ); Tue, 28 Nov 2017 02:19:28 -0500 Received: by mail-pl0-f67.google.com with SMTP id s23so4849386plk.10; Mon, 27 Nov 2017 23:19:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id; bh=aU7GhTE8mq37UDPxsInASET7NjuTCAzYRy4xBQfZ+Tk=; b=PwkLMFywYv7iUx0+34fpCZ37yuLfldQ7FTHcV7QBAB1D9FudQJQBtIjC+fMAaOFDJk sqU20TYbg7QsUHnOeJsrDo8d97w4cG4mZa9LZYYTT+2wEo/jph0piPFkrdWHHi+/hXiu gwRIZzHUhOwzvIQhlRClpc8amr922gMBBGSFxwbmHkntBm4w+2+Ef3Y5KjdYoGPGrMM4 M74SZ6Ie+bne0txFHhgmH6oJANJzJXa+KlfXuUlZxnhxlZg59dZjArxtlFVnaI7aYX61 UnR3GlwCK4Fi6ohnnf6TpUAWjiA/pEnu7PopaMupCQK1Sth7z5Y3aFLDhcc7lFyQauSO AgTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=aU7GhTE8mq37UDPxsInASET7NjuTCAzYRy4xBQfZ+Tk=; b=M+I1P4KA5Efzr+hEr9RmwsanOL1MnqczjH2u+88UiaZ9sVn1aOUMW/BEvbSJjWYNNu IFMk1XjkFYZAjzyb0kcgTBZdGEhwNmI32WgVAKq0IUel4pLzPUtsq2sbxIs4P/u9V1/3 VDK06YB0Rk7P9Qc11Z33iQS1HEOsMVQUm+pb0x4+3ktVSDdmxvtHHDB+lu8MIeeEgHIn hzPcBu7qf9G2DqEOV0QfNHm6S4hVjKB/tfWLIK51yRuBDwMfspQpteBeJsjxzjUGzd/q cT+QtUSCzvfUjscWo8Noy6GXbS9g+cf9LpAH2So//7L7SzBGwzg3NrgFkh9vBhrr2ZlM +uGw== X-Gm-Message-State: AJaThX5LWC6mcnUoQgK/M7h3FPs3PnKaM79OJa5tQwn7wjrF1neC/sqi 5TvV9vfDCsmuYuPETUav1eE= X-Received: by 10.159.244.20 with SMTP id x20mr42007110plr.433.1511853567312; Mon, 27 Nov 2017 23:19:27 -0800 (PST) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id t23sm53283464pfg.97.2017.11.27.23.19.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Nov 2017 23:19:26 -0800 (PST) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Tue, 28 Nov 2017 17:49:16 +1030 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann , =?utf-8?q?C=C3=A9dric_Le_Goater?= Subject: [PATCH v6 0/5] clk: Add Aspeed clock driver Date: Tue, 28 Nov 2017 17:49:03 +1030 Message-Id: <20171128071908.12279-1-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This driver supports the ast2500, ast2400 (and derivative) BMC SoCs from Aspeed. This is v6. See patches for detailed changelogs. v6: Added reviewed-bys v5: Address review from Andrew v4: Address review from Andrew and Stephen. v3: Address review from Andrew and has seen more testing on hardware v2: split the driver out into a series of patches to make them easier to review. All of the important clocks are supported, with most non-essential ones also implemented where information is available. I am working with Aspeed to clear up some of the missing information, including the missing parent-sibling relationships. We need to know the rate of the apb clock in order to correctly program the clocksource driver, so the apb and it's parents are created in the CLK_OF_DECLARE_DRIVER callback. The rest of the clocks are created at normal driver probe time. I followed the Gemini driver's lead with using the regmap where I could, but also having a pointer to the base address for use with the common clock callbacks. The driver borrows from the clk_gate common clock infrastructure, but modifies it in order to support the clock gate and reset pair that most of the clocks have. This pair must be reset-ungated-released, with appropriate delays, according to the datasheet. The first patch introduces the core clock registration parts, and describes the clocks. The second creates the core clocks, giving the system enough to boot (but without uart). Next come the non-core clocks, and finally the reset controller that is used for the few cocks that don't have a gate to go with their reset pair. Please review! Cheers, Joel Joel Stanley (5): clk: Add clock driver for ASPEED BMC SoCs clk: aspeed: Register core clocks clk: aspeed: Add platform driver and register PLLs clk: aspeed: Register gated clocks clk: aspeed: Add reset controller drivers/clk/Kconfig | 12 + drivers/clk/Makefile | 1 + drivers/clk/clk-aspeed.c | 657 +++++++++++++++++++++++++++++++ include/dt-bindings/clock/aspeed-clock.h | 54 +++ 4 files changed, 724 insertions(+) create mode 100644 drivers/clk/clk-aspeed.c create mode 100644 include/dt-bindings/clock/aspeed-clock.h -- 2.14.1