From patchwork Fri Sep 21 15:08:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 147285 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp936767ljw; Fri, 21 Sep 2018 08:11:00 -0700 (PDT) X-Google-Smtp-Source: ANB0VdaGW6JcbJaIks1r1Wii+N9eXbEEKo8CQQE8h3bVkDtDFYONWHWtT69Htwzw7jFlA4mm7PBE X-Received: by 2002:a63:6746:: with SMTP id b67-v6mr6086480pgc.310.1537542660298; Fri, 21 Sep 2018 08:11:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537542660; cv=none; d=google.com; s=arc-20160816; b=nuD9LuBATvlRU4S9uWrfw2VUI2voSO9RggKDFSdzf4XbQ6Ayu0rZQ6+mLaS8MnX9li 08Ku2toUIICWdt1G1OSC/g3bFVhvvmjX6pY2ggmEkEwHVwrMWvJSz1Ij7Q0MpLCl1aKF iHiun9x8S1y9HEpXqP0BQLpPTYxTvDMrbugH6CnYSxXQg9QdPGiW3tF5m5fV9ZokIek9 8k7SJ0zZBIOFkt2/yeG3sVE/Ujsd/kJnmTvKU2qSB+4LMLMFFk/8K+SN3bpA6imf6Be2 8cRyScdI7Ggh82VctT8+cIkc75IxuKHz1fMcObKNHNvFaV4t4Sdbnd6On5m8QBmYbJ2q 3Iqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from; bh=n6ARg2BLmYnZG55IeH2pJrWFJIIfRcZBTmJ2wJpCi4c=; b=mFH9kk6JNQbHPOB8LaGCUHaZEyHvMgo8T6wz0l1qDvVJC4nFSSXJBUWzvGzmgpyoRu IGxWuZuwgb74yr5apb9ixX3EaSHYAO6eJTCmWFtZovhPPAnfJUPXL562Xa0E1mdP0/zA KJ8XPKGo19G8oOhSFAnBUTxMEKNKQGGQaXBzXVhMqrcurjMPx8deKc9AwDkBg1CzMWUM AFPbTbMldUAlIh4zUJ/jYXmIYnFFLVXPLtk0CMezuRg6IPUfz5aqFCW8GYJZq5TihzFA QPq7RZk1yyXeR/KIfOSmUKDo1ZQGaDF2CAOvpbo+Yyx1XEy+pVvEWH5TXcyG6WpmjYOs F5hw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w61-v6si27443526plb.511.2018.09.21.08.10.59; Fri, 21 Sep 2018 08:11:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390560AbeIUVAQ (ORCPT + 32 others); Fri, 21 Sep 2018 17:00:16 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:13097 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2390278AbeIUVAQ (ORCPT ); Fri, 21 Sep 2018 17:00:16 -0400 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 8BB96645FF501; Fri, 21 Sep 2018 23:09:28 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.399.0; Fri, 21 Sep 2018 23:09:24 +0800 From: Shameer Kolothum To: , CC: , , , , , , , , , , , Subject: [PATCH v3 0/3] arm64 SMMUv3 PMU driver with IORT support Date: Fri, 21 Sep 2018 16:08:00 +0100 Message-ID: <20180921150803.25444-1-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds a driver for the SMMUv3 PMU into the perf framework. It includes an IORT update to support PM Counter Groups. This is based on the initial work done by Neil Leeder[1] SMMUv3 PMCG devices are named as smmuv3_pmcg_ where is the physical page address of the SMMU PMCG. For example, the PMCG at 0xff88840000 is named smmuv3_pmcg_ff88840 Usage example: For common arch supported events: perf stat -e smmuv3_pmcg_ff88840/transaction,filter_enable=1, filter_span=1,filter_stream_id=0x42/ -a pwd For IMP DEF events: perf stat -e smmuv3_pmcg_ff88840/event=id/ -a pwd Sanity tested on HiSilicon platform. Further testing on supported platforms are very much welcome. v2 --> v3 -Addressed comments from Robin. -Removed iort helper function to retrieve the PMCG reference smmu. -PMCG devices are now named using the base address v1 --> v2 - Addressed comments from Robin. - Added an helper to retrieve the associated smmu dev and named PMUs to make the association visible to user. - Added MSI support for overflow irq [1]https://www.spinics.net/lists/arm-kernel/msg598591.html Neil Leeder (2): acpi: arm64: add iort support for PMCG perf: add arm64 smmuv3 pmu driver Shameer Kolothum (1): perf/smmuv3: Add MSI irq support drivers/acpi/arm64/iort.c | 78 ++++- drivers/perf/Kconfig | 9 + drivers/perf/Makefile | 1 + drivers/perf/arm_smmuv3_pmu.c | 794 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 870 insertions(+), 12 deletions(-) create mode 100644 drivers/perf/arm_smmuv3_pmu.c -- 2.7.4