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[106.167.171.201]) by smtp.gmail.com with ESMTPSA id c62sm29411952pfb.93.2017.07.17.01.24.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jul 2017 01:24:48 -0700 (PDT) To: "Paul E. McKenney" From: Akira Yokosawa Cc: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Akira Yokosawa Subject: [PATCH] documentation: Fix two-CPU control-dependency example Message-ID: <0d60072f-3848-a2b7-ce18-e1ed317b5c09@gmail.com> Date: Mon, 17 Jul 2017 17:24:42 +0900 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org >From b798b9b631e237d285aa8699da00bfb8ced33bea Mon Sep 17 00:00:00 2001 From: Akira Yokosawa Date: Mon, 17 Jul 2017 16:25:33 +0900 Subject: [PATCH] documentation: Fix two-CPU control-dependency example In commit 5646f7acc95f ("memory-barriers: Fix control-ordering no-transitivity example"), the operator in "if" statement of the two-CPU example was modified from ">=" to ">". Now the example misses the point because there is no party who will modify "x" nor "y". So each CPU performs only the READ_ONCE(). The point of this example is to use control dependency for ordering, and the WRITE_ONCE() should always be executed. So it was correct prior to the above mentioned commit. Partial revert of the commit (with context adjustments regarding other changes thereafter) restores the point. Note that the three-CPU example demonstrating the lack of transitivity stands regardless of this partial revert. Signed-off-by: Akira Yokosawa --- Documentation/memory-barriers.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 Signed-off-by: Boqun Feng diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index c4ddfcd..c1ebe99 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -851,7 +851,7 @@ demonstrated by two related examples, with the initial values of CPU 0 CPU 1 ======================= ======================= r1 = READ_ONCE(x); r2 = READ_ONCE(y); - if (r1 > 0) if (r2 > 0) + if (r1 >= 0) if (r2 >= 0) WRITE_ONCE(y, 1); WRITE_ONCE(x, 1); assert(!(r1 == 1 && r2 == 1));